313a382161
x & (1 << y) is InstCombine's canonical form of a bit test which is currently code generated literally, missing an opportunity to use TBZ/TBNZ on bit 0 of x >> y, which generally results in an instruction sequence that is shorter by 2 instructions. Implement this optimization. On my machine this results in a 0.05% reduction in clang binary size and a 0.25% reduction in dynamic instruction count compiling AArch64ISelLowering.cpp. Reviewers: davemgreen, fhahn Reviewed By: davemgreen Pull Request: https://github.com/llvm/llvm-project/pull/172962
95 lines
2.4 KiB
LLVM
95 lines
2.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
|
|
; RUN: llc --mtriple=aarch64-linux-gnu -o - %s | FileCheck %s
|
|
|
|
declare void @f(i64)
|
|
|
|
define void @bt(i64 %val) {
|
|
; CHECK-LABEL: bt:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov w8, #123 // =0x7b
|
|
; CHECK-NEXT: lsr x8, x8, x0
|
|
; CHECK-NEXT: tbz w8, #0, .LBB0_2
|
|
; CHECK-NEXT: // %bb.1: // %common.ret
|
|
; CHECK-NEXT: ret
|
|
; CHECK-NEXT: .LBB0_2: // %t
|
|
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 16
|
|
; CHECK-NEXT: .cfi_offset w30, -16
|
|
; CHECK-NEXT: mov x0, xzr
|
|
; CHECK-NEXT: bl f
|
|
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
|
|
; CHECK-NEXT: ret
|
|
%shl = shl nuw i64 1, %val
|
|
%and = and i64 %shl, 123
|
|
%cmp = icmp eq i64 %and, 0
|
|
br i1 %cmp, label %t, label %f
|
|
|
|
t:
|
|
call void @f(i64 0)
|
|
ret void
|
|
|
|
f:
|
|
ret void
|
|
}
|
|
|
|
define void @bt_shl_use(i64 %val) {
|
|
; CHECK-LABEL: bt_shl_use:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov w8, #123 // =0x7b
|
|
; CHECK-NEXT: lsr x8, x8, x0
|
|
; CHECK-NEXT: tbz w8, #0, .LBB1_2
|
|
; CHECK-NEXT: // %bb.1: // %common.ret
|
|
; CHECK-NEXT: ret
|
|
; CHECK-NEXT: .LBB1_2: // %t
|
|
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 16
|
|
; CHECK-NEXT: .cfi_offset w30, -16
|
|
; CHECK-NEXT: mov w8, #1 // =0x1
|
|
; CHECK-NEXT: lsl x0, x8, x0
|
|
; CHECK-NEXT: bl f
|
|
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
|
|
; CHECK-NEXT: ret
|
|
%shl = shl nuw i64 1, %val
|
|
%and = and i64 %shl, 123
|
|
%cmp = icmp eq i64 %and, 0
|
|
br i1 %cmp, label %t, label %f
|
|
|
|
t:
|
|
call void @f(i64 %shl)
|
|
ret void
|
|
|
|
f:
|
|
ret void
|
|
}
|
|
|
|
define void @bt_and_use(i64 %val) {
|
|
; CHECK-LABEL: bt_and_use:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov w8, #123 // =0x7b
|
|
; CHECK-NEXT: lsr x9, x8, x0
|
|
; CHECK-NEXT: tbz w9, #0, .LBB2_2
|
|
; CHECK-NEXT: // %bb.1: // %common.ret
|
|
; CHECK-NEXT: ret
|
|
; CHECK-NEXT: .LBB2_2: // %t
|
|
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 16
|
|
; CHECK-NEXT: .cfi_offset w30, -16
|
|
; CHECK-NEXT: mov w9, #1 // =0x1
|
|
; CHECK-NEXT: lsl x9, x9, x0
|
|
; CHECK-NEXT: and x0, x9, x8
|
|
; CHECK-NEXT: bl f
|
|
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
|
|
; CHECK-NEXT: ret
|
|
%shl = shl nuw i64 1, %val
|
|
%and = and i64 %shl, 123
|
|
%cmp = icmp eq i64 %and, 0
|
|
br i1 %cmp, label %t, label %f
|
|
|
|
t:
|
|
call void @f(i64 %and)
|
|
ret void
|
|
|
|
f:
|
|
ret void
|
|
}
|