ad1a45b903
Currently, when SDAG is run on AArch64 and an `optnone` function is encountered, the selector is chosen as FastISel. AArch64 makes use of GlobalISel at O0 and this patch aims to align `optnone` with this functionality. A flag is exposed to enable this functionality for a given backend but, as AArch64 is currently the only backend I could find using GlobalISel at O0 this is the only one with it implemented. This flag is set when the target supports GlobalISel & GlobalISel hasn't been forced by the user, the target machine or by being at an optimisation level lower than `EnableGlobalISelAtO`. If this happens, the GlobalISel passes are included as shown in `llvm/test/CodeGen/AArch64/O3-pipeline.ll` and skipped by IRTranslator for functions not marked as `optnone`. In updating the tests based on this functionality, I found some unused check lines or run lines that mixed SDAG with GlobalISel pass names which have been fixed. --------- Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
106 lines
4.8 KiB
LLVM
106 lines
4.8 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -stop-after=aarch64-isel < %s | FileCheck %s
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%struct.__neon_float32x2x2_t = type { <2 x float>, <2 x float> }
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%struct.__neon_float32x2x3_t = type { <2 x float>, <2 x float>, <2 x float> }
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%struct.__neon_float32x2x4_t = type { <2 x float>, <2 x float>, <2 x float>, <2 x float> }
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declare %struct.__neon_float32x2x2_t @llvm.aarch64.neon.ld2.v2f32.p0(ptr)
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declare %struct.__neon_float32x2x3_t @llvm.aarch64.neon.ld3.v2f32.p0(ptr)
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declare %struct.__neon_float32x2x4_t @llvm.aarch64.neon.ld4.v2f32.p0(ptr)
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declare %struct.__neon_float32x2x2_t @llvm.aarch64.neon.ld1x2.v2f32.p0(ptr)
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declare %struct.__neon_float32x2x3_t @llvm.aarch64.neon.ld1x3.v2f32.p0(ptr)
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declare %struct.__neon_float32x2x4_t @llvm.aarch64.neon.ld1x4.v2f32.p0(ptr)
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declare %struct.__neon_float32x2x2_t @llvm.aarch64.neon.ld2r.v2f32.p0(ptr)
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declare %struct.__neon_float32x2x3_t @llvm.aarch64.neon.ld3r.v2f32.p0(ptr)
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declare %struct.__neon_float32x2x4_t @llvm.aarch64.neon.ld4r.v2f32.p0(ptr)
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declare %struct.__neon_float32x2x2_t @llvm.aarch64.neon.ld2lane.v2f32.p0(<2 x float>, <2 x float>, i64, ptr)
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declare %struct.__neon_float32x2x3_t @llvm.aarch64.neon.ld3lane.v2f32.p0(<2 x float>, <2 x float>, <2 x float>, i64, ptr)
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declare %struct.__neon_float32x2x4_t @llvm.aarch64.neon.ld4lane.v2f32.p0(<2 x float>, <2 x float>, <2 x float>, <2 x float>, i64, ptr)
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define %struct.__neon_float32x2x2_t @test_ld2(ptr %addr) {
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; CHECK-LABEL: name: test_ld2
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; CHECK: LD2Twov2s {{.*}} :: (load (s128) {{.*}})
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%val = call %struct.__neon_float32x2x2_t @llvm.aarch64.neon.ld2.v2f32.p0(ptr %addr)
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ret %struct.__neon_float32x2x2_t %val
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}
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define %struct.__neon_float32x2x3_t @test_ld3(ptr %addr) {
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; CHECK-LABEL: name: test_ld3
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; CHECK: LD3Threev2s {{.*}} :: (load (s192) {{.*}})
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%val = call %struct.__neon_float32x2x3_t @llvm.aarch64.neon.ld3.v2f32.p0(ptr %addr)
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ret %struct.__neon_float32x2x3_t %val
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}
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define %struct.__neon_float32x2x4_t @test_ld4(ptr %addr) {
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; CHECK-LABEL: name: test_ld4
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; CHECK: LD4Fourv2s {{.*}} :: (load (s256) {{.*}})
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%val = call %struct.__neon_float32x2x4_t @llvm.aarch64.neon.ld4.v2f32.p0(ptr %addr)
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ret %struct.__neon_float32x2x4_t %val
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}
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define %struct.__neon_float32x2x2_t @test_ld1x2(ptr %addr) {
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; CHECK-LABEL: name: test_ld1x2
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; CHECK: LD1Twov2s {{.*}} :: (load (s128) {{.*}})
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%val = call %struct.__neon_float32x2x2_t @llvm.aarch64.neon.ld1x2.v2f32.p0(ptr %addr)
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ret %struct.__neon_float32x2x2_t %val
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}
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define %struct.__neon_float32x2x3_t @test_ld1x3(ptr %addr) {
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; CHECK-LABEL: name: test_ld1x3
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; CHECK: LD1Threev2s {{.*}} :: (load (s192) {{.*}})
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%val = call %struct.__neon_float32x2x3_t @llvm.aarch64.neon.ld1x3.v2f32.p0(ptr %addr)
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ret %struct.__neon_float32x2x3_t %val
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}
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define %struct.__neon_float32x2x4_t @test_ld1x4(ptr %addr) {
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; CHECK-LABEL: name: test_ld1x4
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; CHECK: LD1Fourv2s {{.*}} :: (load (s256) {{.*}})
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%val = call %struct.__neon_float32x2x4_t @llvm.aarch64.neon.ld1x4.v2f32.p0(ptr %addr)
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ret %struct.__neon_float32x2x4_t %val
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}
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define %struct.__neon_float32x2x2_t @test_ld2r(ptr %addr) {
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; CHECK-LABEL: name: test_ld2r
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; CHECK: LD2Rv2s {{.*}} :: (load (s64) {{.*}})
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%val = call %struct.__neon_float32x2x2_t @llvm.aarch64.neon.ld2r.v2f32.p0(ptr %addr)
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ret %struct.__neon_float32x2x2_t %val
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}
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define %struct.__neon_float32x2x3_t @test_ld3r(ptr %addr) {
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; CHECK-LABEL: name: test_ld3r
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; CHECK: LD3Rv2s {{.*}} :: (load (s96) {{.*}})
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%val = call %struct.__neon_float32x2x3_t @llvm.aarch64.neon.ld3r.v2f32.p0(ptr %addr)
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ret %struct.__neon_float32x2x3_t %val
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}
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define %struct.__neon_float32x2x4_t @test_ld4r(ptr %addr) {
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; CHECK-LABEL: name: test_ld4r
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; CHECK: LD4Rv2s {{.*}} :: (load (s128) {{.*}})
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%val = call %struct.__neon_float32x2x4_t @llvm.aarch64.neon.ld4r.v2f32.p0(ptr %addr)
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ret %struct.__neon_float32x2x4_t %val
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}
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define %struct.__neon_float32x2x2_t @test_ld2lane(<2 x float> %a, <2 x float> %b, ptr %addr) {
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; CHECK-LABEL: name: test_ld2lane
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; CHECK: {{.*}} LD2i32 {{.*}}
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%val = call %struct.__neon_float32x2x2_t @llvm.aarch64.neon.ld2lane.v2f32.p0(<2 x float> %a, <2 x float> %b, i64 1, ptr %addr)
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ret %struct.__neon_float32x2x2_t %val
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}
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define %struct.__neon_float32x2x3_t @test_ld3lane(<2 x float> %a, <2 x float> %b, <2 x float> %c, ptr %addr) {
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; CHECK-LABEL: name: test_ld3lane
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; CHECK: {{.*}} LD3i32 {{.*}}
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%val = call %struct.__neon_float32x2x3_t @llvm.aarch64.neon.ld3lane.v2f32.p0(<2 x float> %a, <2 x float> %b, <2 x float> %c, i64 1, ptr %addr)
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ret %struct.__neon_float32x2x3_t %val
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}
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define %struct.__neon_float32x2x4_t @test_ld4lane(<2 x float> %a, <2 x float> %b, <2 x float> %c, <2 x float> %d, ptr %addr) {
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; CHECK-LABEL: name: test_ld4lane
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; CHECK: {{.*}} LD4i32 {{.*}}
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%val = call %struct.__neon_float32x2x4_t @llvm.aarch64.neon.ld4lane.v2f32.p0(<2 x float> %a, <2 x float> %b, <2 x float> %c, <2 x float> %d, i64 1, ptr %addr)
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ret %struct.__neon_float32x2x4_t %val
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} |