44b94a4f75
This patch adds the target hooks required by Instruction Referencing for the AArch64 target, as mentioned in https://llvm.org/docs/InstrRefDebugInfo.html#target-hooks Which allows the Instruction Referenced LiveDebugValues Pass to track spills and restore instructions. With this patch we can use the `llvm/utils/llvm-locstats/llvm-locstats.py` to see the coverage statistics on a clang.dSYM built with in RelWithDebInfo we can see: coverage with dbg_value: ``` ================================================= Debug Location Statistics ================================================= cov% samples percentage(~) ------------------------------------------------- 0% 5828021 38% (0%,10%) 127739 0% [10%,20%) 143344 0% [20%,30%) 172100 1% [30%,40%) 193173 1% [40%,50%) 127366 0% [50%,60%) 308350 2% [60%,70%) 257055 1% [70%,80%) 212410 1% [80%,90%) 295316 1% [90%,100%) 349280 2% 100% 7313157 47% ================================================= -the number of debug variables processed: 15327311 -PC ranges covered: 67% ------------------------------------------------- -total availability: 62% ================================================= ``` coverage with InstrRef without target hooks fix: ``` ================================================= Debug Location Statistics ================================================= cov% samples percentage(~) ------------------------------------------------- 0% 6052807 39% (0%,10%) 127710 0% [10%,20%) 129999 0% [20%,30%) 155011 1% [30%,40%) 171206 1% [40%,50%) 102861 0% [50%,60%) 264734 1% [60%,70%) 212386 1% [70%,80%) 176872 1% [80%,90%) 242120 1% [90%,100%) 254465 1% 100% 7437215 48% ================================================= -the number of debug variables processed: 15327386 -PC ranges covered: 67% ------------------------------------------------- -total availability: 60% ================================================= ``` coverage with InstrRef with target hooks fix: ``` ================================================= Debug Location Statistics ================================================= cov% samples percentage(~) ------------------------------------------------- 0% 5972267 39% (0%,10%) 118873 0% [10%,20%) 127138 0% [20%,30%) 153181 1% [30%,40%) 170102 1% [40%,50%) 102180 0% [50%,60%) 263672 1% [60%,70%) 212865 1% [70%,80%) 176633 1% [80%,90%) 242403 1% [90%,100%) 264441 1% 100% 7494527 48% ================================================= -the number of debug variables processed: 15298282 -PC ranges covered: 71% ------------------------------------------------- -total availability: 61% ================================================= ``` I believe this should be a good indication that Instruction Referencing should be turned on for AArch64?
123 lines
4.1 KiB
LLVM
123 lines
4.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc < %s | FileCheck %s
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; Test case to demonstrate a bug where calls to OUTLINED_FUNCTION_1 are
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; inserted at a point where LR is live.
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64"
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define hidden void @_ZTv0_n24_N2C6D1Ev(ptr %this) minsize sspreq "target-features"="+harden-sls-retbr" {
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; CHECK-LABEL: _ZTv0_n24_N2C6D1Ev:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: sub sp, sp, #32
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; CHECK-NEXT: str x30, [sp, #16] // 8-byte Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset w30, -16
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; CHECK-NEXT: bl OUTLINED_FUNCTION_0
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; CHECK-NEXT: b.ne .LBB0_2
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; CHECK-NEXT: // %bb.1: // %entry
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; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Reload
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; CHECK-NEXT: add x0, x0, x8
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; CHECK-NEXT: add sp, sp, #32
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; CHECK-NEXT: b _ZN2C6D1Ev
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; CHECK-NEXT: dsb sy
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; CHECK-NEXT: isb
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; CHECK-NEXT: .LBB0_2: // %entry
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; CHECK-NEXT: bl __stack_chk_fail
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entry:
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%0 = load ptr, ptr %this, align 8
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%1 = getelementptr inbounds i8, ptr %0, i64 -24
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%2 = load i64, ptr %1, align 8
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%3 = getelementptr inbounds i8, ptr %this, i64 %2
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tail call void @_ZN2C6D1Ev(ptr %3)
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ret void
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}
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;
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define hidden void @_ZTv0_n24_N2C6D0Ev(ptr %this) minsize sspreq "target-features"="+harden-sls-retbr" {
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; CHECK-LABEL: _ZTv0_n24_N2C6D0Ev:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: sub sp, sp, #32
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; CHECK-NEXT: str x30, [sp, #16] // 8-byte Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset w30, -16
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; CHECK-NEXT: bl OUTLINED_FUNCTION_0
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; CHECK-NEXT: b.ne .LBB1_2
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; CHECK-NEXT: // %bb.1: // %entry
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; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Reload
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; CHECK-NEXT: add x0, x0, x8
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; CHECK-NEXT: add sp, sp, #32
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; CHECK-NEXT: b _ZN2C6D0Ev
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; CHECK-NEXT: dsb sy
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; CHECK-NEXT: isb
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; CHECK-NEXT: .LBB1_2: // %entry
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; CHECK-NEXT: bl __stack_chk_fail
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entry:
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%0 = load ptr, ptr %this, align 8
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%1 = getelementptr inbounds i8, ptr %0, i64 -24
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%2 = load i64, ptr %1, align 8
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%3 = getelementptr inbounds i8, ptr %this, i64 %2
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tail call void @_ZN2C6D0Ev(ptr %3)
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ret void
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}
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define hidden void @_ZTv0_n24_N3C10D1Ev(ptr %this) minsize sspreq "target-features"="+harden-sls-retbr" {
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; CHECK-LABEL: _ZTv0_n24_N3C10D1Ev:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: sub sp, sp, #32
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; CHECK-NEXT: str x30, [sp, #16] // 8-byte Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset w30, -16
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; CHECK-NEXT: bl OUTLINED_FUNCTION_0
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; CHECK-NEXT: b.ne .LBB2_2
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; CHECK-NEXT: // %bb.1: // %entry
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; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Reload
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; CHECK-NEXT: add x0, x0, x8
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; CHECK-NEXT: add sp, sp, #32
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; CHECK-NEXT: b _ZN3C10D1Ev
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; CHECK-NEXT: dsb sy
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; CHECK-NEXT: isb
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; CHECK-NEXT: .LBB2_2: // %entry
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; CHECK-NEXT: bl __stack_chk_fail
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entry:
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%0 = load ptr, ptr %this, align 8
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%1 = getelementptr inbounds i8, ptr %0, i64 -24
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%2 = load i64, ptr %1, align 8
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%3 = getelementptr inbounds i8, ptr %this, i64 %2
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tail call void @_ZN3C10D1Ev(ptr %3)
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ret void
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}
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define hidden void @_ZTv0_n24_N3C10D0Ev(ptr %this) minsize sspreq "target-features"="+harden-sls-retbr" {
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; CHECK-LABEL: _ZTv0_n24_N3C10D0Ev:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: sub sp, sp, #32
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; CHECK-NEXT: str x30, [sp, #16] // 8-byte Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset w30, -16
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; CHECK-NEXT: bl OUTLINED_FUNCTION_0
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; CHECK-NEXT: b.ne .LBB3_2
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; CHECK-NEXT: // %bb.1: // %entry
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; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Reload
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; CHECK-NEXT: add x0, x0, x8
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; CHECK-NEXT: add sp, sp, #32
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; CHECK-NEXT: b _ZN3C10D0Ev
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; CHECK-NEXT: dsb sy
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; CHECK-NEXT: isb
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; CHECK-NEXT: .LBB3_2: // %entry
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; CHECK-NEXT: bl __stack_chk_fail
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entry:
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%0 = load ptr, ptr %this, align 8
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%1 = getelementptr inbounds i8, ptr %0, i64 -24
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%2 = load i64, ptr %1, align 8
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%3 = getelementptr inbounds i8, ptr %this, i64 %2
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tail call void @_ZN3C10D0Ev(ptr %3)
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ret void
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}
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declare void @_ZN2C6D1Ev(ptr %this)
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declare void @_ZN3C10D1Ev(ptr %this)
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declare void @_ZN2C6D0Ev(ptr %this)
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declare void @_ZN3C10D0Ev(ptr %this)
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