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llvm-project/llvm/test/CodeGen/AArch64/stack-hazard-windows.ll
Shubham Sandeep Rastogi 44b94a4f75
[AArch64][DebugInfo]Add Target hooks for InstrRef on AArch64 (#165953) 
This patch adds the target hooks required by Instruction Referencing for
the AArch64 target, as mentioned in
https://llvm.org/docs/InstrRefDebugInfo.html#target-hooks

Which allows the Instruction Referenced LiveDebugValues Pass to track
spills and restore instructions.

With this patch we can use the
`llvm/utils/llvm-locstats/llvm-locstats.py` to see the coverage
statistics on a clang.dSYM built with in RelWithDebInfo we can see:

coverage with dbg_value:
```
=================================================
            Debug Location Statistics       
 =================================================
     cov%           samples         percentage(~)  
 -------------------------------------------------
   0%              5828021               38%
   (0%,10%)         127739                0%
   [10%,20%)        143344                0%
   [20%,30%)        172100                1%
   [30%,40%)        193173                1%
   [40%,50%)        127366                0%
   [50%,60%)        308350                2%
   [60%,70%)        257055                1%
   [70%,80%)        212410                1%
   [80%,90%)        295316                1%
   [90%,100%)       349280                2%
   100%            7313157               47%
 =================================================
 -the number of debug variables processed: 15327311
 -PC ranges covered: 67%
 -------------------------------------------------
 -total availability: 62%
 =================================================
 ```
 
coverage with InstrRef without target hooks fix:
```
 =================================================
            Debug Location Statistics       
 =================================================
     cov%           samples         percentage(~)  
 -------------------------------------------------
   0%              6052807               39%
   (0%,10%)         127710                0%
   [10%,20%)        129999                0%
   [20%,30%)        155011                1%
   [30%,40%)        171206                1%
   [40%,50%)        102861                0%
   [50%,60%)        264734                1%
   [60%,70%)        212386                1%
   [70%,80%)        176872                1%
   [80%,90%)        242120                1%
   [90%,100%)       254465                1%
   100%            7437215               48%
 =================================================
 -the number of debug variables processed: 15327386
 -PC ranges covered: 67%
 -------------------------------------------------
 -total availability: 60%
 =================================================
 ```
 
coverage with InstrRef with target hooks fix:
```
 =================================================
            Debug Location Statistics       
 =================================================
     cov%           samples         percentage(~)  
 -------------------------------------------------
   0%              5972267               39%
   (0%,10%)         118873                0%
   [10%,20%)        127138                0%
   [20%,30%)        153181                1%
   [30%,40%)        170102                1%
   [40%,50%)        102180                0%
   [50%,60%)        263672                1%
   [60%,70%)        212865                1%
   [70%,80%)        176633                1%
   [80%,90%)        242403                1%
   [90%,100%)       264441                1%
   100%            7494527               48%
 =================================================
 -the number of debug variables processed: 15298282
 -PC ranges covered: 71%
 -------------------------------------------------
 -total availability: 61%
 =================================================
 ```
 
 I believe this should be a good indication that Instruction Referencing should be turned on for AArch64?
2025-11-14 10:36:47 -08:00

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=aarch64-windows-pc-msvc -aarch64-stack-hazard-size=0 | FileCheck %s --check-prefixes=CHECK0
; RUN: llc < %s -mtriple=aarch64-windows-pc-msvc -aarch64-stack-hazard-size=64 | FileCheck %s --check-prefixes=CHECK64
; RUN: llc < %s -mtriple=aarch64-windows-pc-msvc -aarch64-stack-hazard-size=1024 | FileCheck %s --check-prefixes=CHECK1024
define i32 @fpr_csr_stackobj(double %x) "aarch64_pstate_sm_compatible" "frame-pointer"="all" {
; CHECK0-LABEL: fpr_csr_stackobj:
; CHECK0: .seh_proc fpr_csr_stackobj
; CHECK0-NEXT: // %bb.0: // %entry
; CHECK0-NEXT: str x23, [sp, #-48]! // 8-byte Folded Spill
; CHECK0-NEXT: .seh_save_reg_x x23, 48
; CHECK0-NEXT: stp x29, x30, [sp, #8] // 16-byte Folded Spill
; CHECK0-NEXT: .seh_save_fplr 8
; CHECK0-NEXT: stp d9, d10, [sp, #24] // 16-byte Folded Spill
; CHECK0-NEXT: .seh_save_fregp d9, 24
; CHECK0-NEXT: add x29, sp, #8
; CHECK0-NEXT: .seh_add_fp 8
; CHECK0-NEXT: .seh_endprologue
; CHECK0-NEXT: mov w0, wzr
; CHECK0-NEXT: //APP
; CHECK0-NEXT: //NO_APP
; CHECK0-NEXT: str d0, [x29, #32]
; CHECK0-NEXT: .seh_startepilogue
; CHECK0-NEXT: ldp d9, d10, [sp, #24] // 16-byte Folded Reload
; CHECK0-NEXT: .seh_save_fregp d9, 24
; CHECK0-NEXT: ldp x29, x30, [sp, #8] // 16-byte Folded Reload
; CHECK0-NEXT: .seh_save_fplr 8
; CHECK0-NEXT: ldr x23, [sp], #48 // 8-byte Folded Reload
; CHECK0-NEXT: .seh_save_reg_x x23, 48
; CHECK0-NEXT: .seh_endepilogue
; CHECK0-NEXT: ret
; CHECK0-NEXT: .seh_endfunclet
; CHECK0-NEXT: .seh_endproc
;
; CHECK64-LABEL: fpr_csr_stackobj:
; CHECK64: .seh_proc fpr_csr_stackobj
; CHECK64-NEXT: // %bb.0: // %entry
; CHECK64-NEXT: sub sp, sp, #192
; CHECK64-NEXT: .seh_stackalloc 192
; CHECK64-NEXT: str x23, [sp, #80] // 8-byte Spill
; CHECK64-NEXT: .seh_save_reg x23, 80
; CHECK64-NEXT: str x29, [sp, #88] // 8-byte Spill
; CHECK64-NEXT: .seh_save_reg x29, 88
; CHECK64-NEXT: str x30, [sp, #96] // 8-byte Spill
; CHECK64-NEXT: .seh_save_reg x30, 96
; CHECK64-NEXT: str d9, [sp, #168] // 8-byte Spill
; CHECK64-NEXT: .seh_save_freg d9, 168
; CHECK64-NEXT: str d10, [sp, #176] // 8-byte Spill
; CHECK64-NEXT: .seh_save_freg d10, 176
; CHECK64-NEXT: add x29, sp, #88
; CHECK64-NEXT: .seh_add_fp 88
; CHECK64-NEXT: .seh_endprologue
; CHECK64-NEXT: mov w0, wzr
; CHECK64-NEXT: //APP
; CHECK64-NEXT: //NO_APP
; CHECK64-NEXT: stur d0, [x29, #-16]
; CHECK64-NEXT: .seh_startepilogue
; CHECK64-NEXT: ldr d10, [sp, #176] // 8-byte Reload
; CHECK64-NEXT: .seh_save_freg d10, 176
; CHECK64-NEXT: ldr d9, [sp, #168] // 8-byte Reload
; CHECK64-NEXT: .seh_save_freg d9, 168
; CHECK64-NEXT: ldr x30, [sp, #96] // 8-byte Reload
; CHECK64-NEXT: .seh_save_reg x30, 96
; CHECK64-NEXT: ldr x29, [sp, #88] // 8-byte Reload
; CHECK64-NEXT: .seh_save_reg x29, 88
; CHECK64-NEXT: ldr x23, [sp, #80] // 8-byte Reload
; CHECK64-NEXT: .seh_save_reg x23, 80
; CHECK64-NEXT: add sp, sp, #192
; CHECK64-NEXT: .seh_stackalloc 192
; CHECK64-NEXT: .seh_endepilogue
; CHECK64-NEXT: ret
; CHECK64-NEXT: .seh_endfunclet
; CHECK64-NEXT: .seh_endproc
;
; CHECK1024-LABEL: fpr_csr_stackobj:
; CHECK1024: .seh_proc fpr_csr_stackobj
; CHECK1024-NEXT: // %bb.0: // %entry
; CHECK1024-NEXT: sub sp, sp, #1072
; CHECK1024-NEXT: .seh_stackalloc 1072
; CHECK1024-NEXT: str x23, [sp] // 8-byte Spill
; CHECK1024-NEXT: .seh_save_reg x23, 0
; CHECK1024-NEXT: str x29, [sp, #8] // 8-byte Spill
; CHECK1024-NEXT: .seh_save_reg x29, 8
; CHECK1024-NEXT: str x30, [sp, #16] // 8-byte Spill
; CHECK1024-NEXT: .seh_save_reg x30, 16
; CHECK1024-NEXT: str d9, [sp, #1048] // 8-byte Spill
; CHECK1024-NEXT: .seh_save_freg d9, 1048
; CHECK1024-NEXT: str d10, [sp, #1056] // 8-byte Spill
; CHECK1024-NEXT: .seh_save_freg d10, 1056
; CHECK1024-NEXT: add x29, sp, #8
; CHECK1024-NEXT: .seh_add_fp 8
; CHECK1024-NEXT: .seh_endprologue
; CHECK1024-NEXT: sub sp, sp, #1040
; CHECK1024-NEXT: mov w0, wzr
; CHECK1024-NEXT: //APP
; CHECK1024-NEXT: //NO_APP
; CHECK1024-NEXT: stur d0, [x29, #-16]
; CHECK1024-NEXT: .seh_startepilogue
; CHECK1024-NEXT: add sp, sp, #1040
; CHECK1024-NEXT: .seh_stackalloc 1040
; CHECK1024-NEXT: ldr d10, [sp, #1056] // 8-byte Reload
; CHECK1024-NEXT: .seh_save_freg d10, 1056
; CHECK1024-NEXT: ldr d9, [sp, #1048] // 8-byte Reload
; CHECK1024-NEXT: .seh_save_freg d9, 1048
; CHECK1024-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK1024-NEXT: .seh_save_reg x30, 16
; CHECK1024-NEXT: ldr x29, [sp, #8] // 8-byte Reload
; CHECK1024-NEXT: .seh_save_reg x29, 8
; CHECK1024-NEXT: ldr x23, [sp] // 8-byte Reload
; CHECK1024-NEXT: .seh_save_reg x23, 0
; CHECK1024-NEXT: add sp, sp, #1072
; CHECK1024-NEXT: .seh_stackalloc 1072
; CHECK1024-NEXT: .seh_endepilogue
; CHECK1024-NEXT: ret
; CHECK1024-NEXT: .seh_endfunclet
; CHECK1024-NEXT: .seh_endproc
entry:
%a = alloca double
tail call void asm sideeffect "", "~{x23},~{d9},~{d10}"()
store double %x, ptr %a
ret i32 0
}
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