e958bcdd17
This patch fixes a regression introduced by PR #175022, where a freeze was introduced with the following transformation: ext(freeze(load(x))) -> freeze(extload(x)) If a new extend is introduced afterwards we then have ext(freeze(extload(x))) which doesn't get picked up by existing DAG combines due to the freeze getting in the way.
235 lines
7.4 KiB
LLVM
235 lines
7.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,X86
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,X64
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define void @knownbits_zext_in_reg(ptr) nounwind {
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; X86-LABEL: knownbits_zext_in_reg:
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; X86: # %bb.0: # %BB
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; X86-NEXT: pushl %ebx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movzbl (%eax), %ecx
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; X86-NEXT: imull $101, %ecx, %eax
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; X86-NEXT: shrl $14, %eax
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; X86-NEXT: imull $177, %ecx, %edx
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; X86-NEXT: shrl $14, %edx
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; X86-NEXT: movzbl %al, %ecx
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; X86-NEXT: xorl %ebx, %ebx
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; X86-NEXT: .p2align 4
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; X86-NEXT: .LBB0_1: # %CF
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; X86-NEXT: # =>This Loop Header: Depth=1
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; X86-NEXT: # Child Loop BB0_2 Depth 2
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; X86-NEXT: movl %ecx, %eax
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; X86-NEXT: divb %dl
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; X86-NEXT: .p2align 4
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; X86-NEXT: .LBB0_2: # %CF237
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; X86-NEXT: # Parent Loop BB0_1 Depth=1
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; X86-NEXT: # => This Inner Loop Header: Depth=2
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; X86-NEXT: testb %bl, %bl
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; X86-NEXT: jne .LBB0_2
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; X86-NEXT: jmp .LBB0_1
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;
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; X64-LABEL: knownbits_zext_in_reg:
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; X64: # %bb.0: # %BB
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; X64-NEXT: movzbl (%rdi), %eax
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; X64-NEXT: imull $101, %eax, %ecx
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; X64-NEXT: shrl $14, %ecx
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; X64-NEXT: imull $177, %eax, %edx
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; X64-NEXT: shrl $14, %edx
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; X64-NEXT: movzbl %cl, %ecx
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; X64-NEXT: xorl %esi, %esi
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; X64-NEXT: .p2align 4
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; X64-NEXT: .LBB0_1: # %CF
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; X64-NEXT: # =>This Loop Header: Depth=1
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; X64-NEXT: # Child Loop BB0_2 Depth 2
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; X64-NEXT: movl %ecx, %eax
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; X64-NEXT: divb %dl
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; X64-NEXT: .p2align 4
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; X64-NEXT: .LBB0_2: # %CF237
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; X64-NEXT: # Parent Loop BB0_1 Depth=1
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; X64-NEXT: # => This Inner Loop Header: Depth=2
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; X64-NEXT: testb %sil, %sil
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; X64-NEXT: jne .LBB0_2
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; X64-NEXT: jmp .LBB0_1
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BB:
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%L5 = load i8, ptr %0
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%Sl9 = select i1 true, i8 %L5, i8 undef
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%B21 = udiv i8 %Sl9, -93
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%B22 = udiv i8 %Sl9, 93
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br label %CF
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CF: ; preds = %CF246, %BB
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%I40 = insertelement <4 x i8> zeroinitializer, i8 %B21, i32 1
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%I41 = insertelement <4 x i8> zeroinitializer, i8 %B22, i32 1
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%B41 = srem <4 x i8> %I40, %I41
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br label %CF237
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CF237: ; preds = %CF237, %CF
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%Cmp73 = icmp ne i1 undef, undef
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br i1 %Cmp73, label %CF237, label %CF246
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CF246: ; preds = %CF237
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%Cmp117 = icmp ult <4 x i8> %B41, undef
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%E156 = extractelement <4 x i1> %Cmp117, i32 2
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br label %CF
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}
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define i32 @knownbits_mask_add_lshr(i32 %a0, i32 %a1) nounwind {
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; CHECK-LABEL: knownbits_mask_add_lshr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: ret{{[l|q]}}
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%1 = and i32 %a0, 32767
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%2 = and i32 %a1, 32766
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%3 = add i32 %1, %2
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%4 = lshr i32 %3, 17
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ret i32 %4
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}
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define i128 @knownbits_mask_addc_shl(i64 %a0, i64 %a1, i64 %a2) nounwind {
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; X86-LABEL: knownbits_mask_addc_shl:
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; X86: # %bb.0:
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; X86-NEXT: pushl %edi
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl $-1024, %esi # imm = 0xFC00
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
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; X86-NEXT: andl %esi, %edi
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; X86-NEXT: andl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: addl %edi, %esi
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; X86-NEXT: adcl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: adcl $0, %ecx
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; X86-NEXT: shldl $22, %edx, %ecx
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; X86-NEXT: shldl $22, %esi, %edx
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; X86-NEXT: movl %edx, 8(%eax)
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; X86-NEXT: movl %ecx, 12(%eax)
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; X86-NEXT: movl $0, 4(%eax)
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; X86-NEXT: movl $0, (%eax)
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; X86-NEXT: popl %esi
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; X86-NEXT: popl %edi
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; X86-NEXT: retl $4
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;
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; X64-LABEL: knownbits_mask_addc_shl:
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; X64: # %bb.0:
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; X64-NEXT: andq $-1024, %rdi # imm = 0xFC00
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; X64-NEXT: andq $-1024, %rsi # imm = 0xFC00
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; X64-NEXT: addq %rdi, %rsi
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; X64-NEXT: adcl $0, %edx
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; X64-NEXT: shldq $54, %rsi, %rdx
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: retq
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%1 = and i64 %a0, -1024
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%2 = zext i64 %1 to i128
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%3 = and i64 %a1, -1024
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%4 = zext i64 %3 to i128
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%5 = add i128 %2, %4
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%6 = zext i64 %a2 to i128
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%7 = shl i128 %6, 64
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%8 = add i128 %5, %7
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%9 = shl i128 %8, 54
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ret i128 %9
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}
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define {i32, i1} @knownbits_uaddo_saddo(i64 %a0, i64 %a1) nounwind {
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; X86-LABEL: knownbits_uaddo_saddo:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: addl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: setb %al
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; X86-NEXT: seto %dl
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; X86-NEXT: orb %al, %dl
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; X86-NEXT: xorl %eax, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: knownbits_uaddo_saddo:
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; X64: # %bb.0:
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; X64-NEXT: shlq $32, %rdi
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; X64-NEXT: shlq $32, %rsi
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; X64-NEXT: addq %rdi, %rsi
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; X64-NEXT: setb %al
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; X64-NEXT: seto %dl
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; X64-NEXT: orb %al, %dl
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: retq
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%1 = shl i64 %a0, 32
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%2 = shl i64 %a1, 32
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%u = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %1, i64 %2)
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%uval = extractvalue {i64, i1} %u, 0
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%uovf = extractvalue {i64, i1} %u, 1
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%s = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %1, i64 %2)
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%sval = extractvalue {i64, i1} %s, 0
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%sovf = extractvalue {i64, i1} %s, 1
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%sum = add i64 %uval, %sval
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%3 = trunc i64 %sum to i32
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%4 = or i1 %uovf, %sovf
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%ret0 = insertvalue {i32, i1} undef, i32 %3, 0
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%ret1 = insertvalue {i32, i1} %ret0, i1 %4, 1
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ret {i32, i1} %ret1
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}
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define {i32, i1} @knownbits_usubo_ssubo(i64 %a0, i64 %a1) nounwind {
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; X86-LABEL: knownbits_usubo_ssubo:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: cmpl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: setb %al
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; X86-NEXT: seto %dl
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; X86-NEXT: orb %al, %dl
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; X86-NEXT: xorl %eax, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: knownbits_usubo_ssubo:
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; X64: # %bb.0:
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; X64-NEXT: shlq $32, %rdi
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; X64-NEXT: shlq $32, %rsi
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; X64-NEXT: cmpq %rsi, %rdi
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; X64-NEXT: setb %al
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; X64-NEXT: seto %dl
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; X64-NEXT: orb %al, %dl
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: retq
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%1 = shl i64 %a0, 32
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%2 = shl i64 %a1, 32
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%u = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %1, i64 %2)
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%uval = extractvalue {i64, i1} %u, 0
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%uovf = extractvalue {i64, i1} %u, 1
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%s = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %1, i64 %2)
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%sval = extractvalue {i64, i1} %s, 0
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%sovf = extractvalue {i64, i1} %s, 1
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%sum = add i64 %uval, %sval
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%3 = trunc i64 %sum to i32
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%4 = or i1 %uovf, %sovf
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%ret0 = insertvalue {i32, i1} undef, i32 %3, 0
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%ret1 = insertvalue {i32, i1} %ret0, i1 %4, 1
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ret {i32, i1} %ret1
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}
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declare {i64, i1} @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
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declare {i64, i1} @llvm.sadd.with.overflow.i64(i64, i64) nounwind readnone
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declare {i64, i1} @llvm.usub.with.overflow.i64(i64, i64) nounwind readnone
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declare {i64, i1} @llvm.ssub.with.overflow.i64(i64, i64) nounwind readnone
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define i32 @knownbits_fshl(i32 %a0) nounwind {
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; CHECK-LABEL: knownbits_fshl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl $3, %eax
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; CHECK-NEXT: ret{{[l|q]}}
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%1 = tail call i32 @llvm.fshl.i32(i32 %a0, i32 -1, i32 5)
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%2 = and i32 %1, 3
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ret i32 %2
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}
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define i32 @knownbits_fshr(i32 %a0) nounwind {
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; CHECK-LABEL: knownbits_fshr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl $3, %eax
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; CHECK-NEXT: ret{{[l|q]}}
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%1 = tail call i32 @llvm.fshr.i32(i32 %a0, i32 -1, i32 5)
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%2 = and i32 %1, 3
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ret i32 %2
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}
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declare i32 @llvm.fshl.i32(i32, i32, i32) nounwind readnone
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declare i32 @llvm.fshr.i32(i32, i32, i32) nounwind readnone
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