02d3738be9
getVectorInstrCostHelper would return costs of zero for vector inserts/extracts that move data between GPR and vector registers, if there was no 'real' use, i.e. there was no corresponding existing instruction. This meant that passes like LoopVectorize and SLPVectorizer, which likely are the main users of the interface, would understimate the cost of insert/extracts that move data between GPR and vector registers, which has non-trivial costs. The patch removes the special case and only returns costs of zero for lane 0 if it there is no need to transfer between integer and vector registers. This impacts a number of SLP test, and most of them look like general improvements.I think the change should make things more accurate for any AArch64 target, but if not it could also just be Apple CPU specific. I am seeing +2% end-to-end improvements on SLP-heavy workloads. PR: https://github.com/llvm/llvm-project/pull/146526
87 lines
2.5 KiB
LLVM
87 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt -passes=slp-vectorizer -S -slp-threshold=-99999 -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
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define void @test() {
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; CHECK-LABEL: define void @test() {
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; CHECK-NEXT: bb:
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; CHECK-NEXT: br label [[BB1:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: [[PHI7:%.*]] = phi i32 [ 0, [[BB10:%.*]] ], [ 0, [[BB:%.*]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = phi <8 x i32> [ poison, [[BB10]] ], [ zeroinitializer, [[BB]] ]
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; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> <i32 poison, i32 undef>, i32 [[PHI7]], i32 0
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; CHECK-NEXT: switch i32 0, label [[BB16:%.*]] [
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; CHECK-NEXT: i32 0, label [[BB14:%.*]]
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; CHECK-NEXT: i32 1, label [[BB11:%.*]]
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; CHECK-NEXT: ]
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; CHECK: bb9:
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; CHECK-NEXT: br label [[BB11]]
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; CHECK: bb10:
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; CHECK-NEXT: br label [[BB1]]
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; CHECK: bb11:
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; CHECK-NEXT: [[TMP2:%.*]] = phi <2 x i32> [ poison, [[BB9:%.*]] ], [ [[TMP1]], [[BB1]] ]
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; CHECK-NEXT: ret void
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; CHECK: bb14:
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; CHECK-NEXT: ret void
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; CHECK: bb15:
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; CHECK-NEXT: ret void
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; CHECK: bb16:
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; CHECK-NEXT: [[TMP3:%.*]] = phi <8 x i32> [ [[TMP0]], [[BB1]] ], [ poison, [[BB25:%.*]] ]
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; CHECK-NEXT: ret void
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; CHECK: bb25:
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; CHECK-NEXT: switch i32 0, label [[BB16]] [
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; CHECK-NEXT: i32 0, label [[BB14]]
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; CHECK-NEXT: i32 1, label [[BB15:%.*]]
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; CHECK-NEXT: ]
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;
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bb:
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br label %bb1
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bb1:
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%phi = phi i32 [ 0, %bb10 ], [ 0, %bb ]
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%phi2 = phi i32 [ 0, %bb10 ], [ 0, %bb ]
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%phi3 = phi i32 [ 0, %bb10 ], [ 0, %bb ]
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%phi4 = phi i32 [ 0, %bb10 ], [ 0, %bb ]
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%phi5 = phi i32 [ 0, %bb10 ], [ 0, %bb ]
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%phi6 = phi i32 [ 0, %bb10 ], [ 0, %bb ]
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%phi7 = phi i32 [ 0, %bb10 ], [ 0, %bb ]
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%phi8 = phi i32 [ 0, %bb10 ], [ 0, %bb ]
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switch i32 0, label %bb16 [
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i32 0, label %bb14
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i32 1, label %bb11
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]
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bb9:
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br label %bb11
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bb10:
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br label %bb1
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bb11:
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%phi12 = phi i32 [ 0, %bb9 ], [ %phi7, %bb1 ]
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%phi13 = phi i32 [ 0, %bb9 ], [ undef, %bb1 ]
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ret void
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bb14:
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ret void
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bb15:
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ret void
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bb16:
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%phi17 = phi i32 [ %phi, %bb1 ], [ 0, %bb25 ]
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%phi18 = phi i32 [ %phi2, %bb1 ], [ 0, %bb25 ]
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%phi19 = phi i32 [ %phi3, %bb1 ], [ 0, %bb25 ]
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%phi20 = phi i32 [ %phi4, %bb1 ], [ 0, %bb25 ]
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%phi21 = phi i32 [ %phi5, %bb1 ], [ 0, %bb25 ]
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%phi22 = phi i32 [ %phi6, %bb1 ], [ 0, %bb25 ]
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%phi23 = phi i32 [ %phi7, %bb1 ], [ 0, %bb25 ]
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%phi24 = phi i32 [ %phi8, %bb1 ], [ 0, %bb25 ]
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ret void
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bb25:
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switch i32 0, label %bb16 [
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i32 0, label %bb14
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i32 1, label %bb15
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]
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}
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