15b9109bc7
This is needed to support functionality in the AMDGPU scheduler. Various passes have been modified to preserve MBFI to ensure that this change does not introduce new invocations of MBFI. Some targets have passes reordered, but there are no new runs of MBFI.
247 lines
8.9 KiB
C++
247 lines
8.9 KiB
C++
//===-- UnreachableBlockElim.cpp - Remove unreachable blocks for codegen --===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass is an extremely simple version of the SimplifyCFG pass. Its sole
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// job is to delete LLVM basic blocks that are not reachable from the entry
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// node. To do this, it performs a simple depth first traversal of the CFG,
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// then deletes any unvisited nodes.
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//
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// Note that this pass is really a hack. In particular, the instruction
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// selectors for various targets should just not generate code for unreachable
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// blocks. Until LLVM has a more systematic way of defining instruction
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// selectors, however, we cannot really expect them to handle additional
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// complexity.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/UnreachableBlockElim.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachinePostDominators.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/IR/Dominators.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/Pass.h"
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#include "llvm/Transforms/Utils/BasicBlockUtils.h"
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using namespace llvm;
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namespace {
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class UnreachableBlockElimLegacyPass : public FunctionPass {
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bool runOnFunction(Function &F) override {
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return llvm::EliminateUnreachableBlocks(F);
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}
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public:
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static char ID; // Pass identification, replacement for typeid
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UnreachableBlockElimLegacyPass() : FunctionPass(ID) {
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initializeUnreachableBlockElimLegacyPassPass(
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*PassRegistry::getPassRegistry());
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addPreserved<DominatorTreeWrapperPass>();
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AU.addPreserved<MachineBlockFrequencyInfoWrapperPass>();
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}
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};
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}
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char UnreachableBlockElimLegacyPass::ID = 0;
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INITIALIZE_PASS(UnreachableBlockElimLegacyPass, "unreachableblockelim",
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"Remove unreachable blocks from the CFG", false, false)
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FunctionPass *llvm::createUnreachableBlockEliminationPass() {
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return new UnreachableBlockElimLegacyPass();
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}
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PreservedAnalyses UnreachableBlockElimPass::run(Function &F,
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FunctionAnalysisManager &AM) {
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bool Changed = llvm::EliminateUnreachableBlocks(F);
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if (!Changed)
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return PreservedAnalyses::all();
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PreservedAnalyses PA;
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PA.preserve<DominatorTreeAnalysis>();
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PA.preserve<MachineBlockFrequencyAnalysis>();
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return PA;
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}
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namespace {
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class UnreachableMachineBlockElim {
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MachineDominatorTree *MDT;
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MachinePostDominatorTree *MPDT;
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MachineLoopInfo *MLI;
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public:
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UnreachableMachineBlockElim(MachineDominatorTree *MDT,
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MachinePostDominatorTree *MPDT,
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MachineLoopInfo *MLI)
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: MDT(MDT), MPDT(MPDT), MLI(MLI) {}
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bool run(MachineFunction &MF);
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};
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class UnreachableMachineBlockElimLegacy : public MachineFunctionPass {
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bool runOnMachineFunction(MachineFunction &F) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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public:
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static char ID; // Pass identification, replacement for typeid
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UnreachableMachineBlockElimLegacy() : MachineFunctionPass(ID) {}
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};
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} // namespace
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char UnreachableMachineBlockElimLegacy::ID = 0;
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INITIALIZE_PASS(UnreachableMachineBlockElimLegacy,
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"unreachable-mbb-elimination",
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"Remove unreachable machine basic blocks", false, false)
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char &llvm::UnreachableMachineBlockElimID =
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UnreachableMachineBlockElimLegacy::ID;
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void UnreachableMachineBlockElimLegacy::getAnalysisUsage(
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AnalysisUsage &AU) const {
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AU.addPreserved<MachineLoopInfoWrapperPass>();
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AU.addPreserved<MachineDominatorTreeWrapperPass>();
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AU.addPreserved<MachinePostDominatorTreeWrapperPass>();
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AU.addPreserved<MachineBlockFrequencyInfoWrapperPass>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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PreservedAnalyses
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UnreachableMachineBlockElimPass::run(MachineFunction &MF,
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MachineFunctionAnalysisManager &AM) {
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auto *MDT = AM.getCachedResult<MachineDominatorTreeAnalysis>(MF);
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auto *MPDT = AM.getCachedResult<MachinePostDominatorTreeAnalysis>(MF);
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auto *MLI = AM.getCachedResult<MachineLoopAnalysis>(MF);
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if (!UnreachableMachineBlockElim(MDT, MPDT, MLI).run(MF))
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return PreservedAnalyses::all();
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return getMachineFunctionPassPreservedAnalyses()
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.preserve<MachineLoopAnalysis>()
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.preserve<MachineDominatorTreeAnalysis>()
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.preserve<MachinePostDominatorTreeAnalysis>()
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.preserve<MachineBlockFrequencyAnalysis>();
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}
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bool UnreachableMachineBlockElimLegacy::runOnMachineFunction(
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MachineFunction &MF) {
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MachineDominatorTreeWrapperPass *MDTWrapper =
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getAnalysisIfAvailable<MachineDominatorTreeWrapperPass>();
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MachinePostDominatorTreeWrapperPass *MPDTWrapper =
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getAnalysisIfAvailable<MachinePostDominatorTreeWrapperPass>();
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MachineDominatorTree *MDT = MDTWrapper ? &MDTWrapper->getDomTree() : nullptr;
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MachinePostDominatorTree *MPDT =
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MPDTWrapper ? &MPDTWrapper->getPostDomTree() : nullptr;
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MachineLoopInfoWrapperPass *MLIWrapper =
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getAnalysisIfAvailable<MachineLoopInfoWrapperPass>();
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MachineLoopInfo *MLI = MLIWrapper ? &MLIWrapper->getLI() : nullptr;
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return UnreachableMachineBlockElim(MDT, MPDT, MLI).run(MF);
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}
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bool UnreachableMachineBlockElim::run(MachineFunction &F) {
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df_iterator_default_set<MachineBasicBlock *> Reachable;
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bool ModifiedPHI = false;
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// Mark all reachable blocks.
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for (MachineBasicBlock *BB : depth_first_ext(&F, Reachable))
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(void)BB/* Mark all reachable blocks */;
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// Loop over all dead blocks, remembering them and deleting all instructions
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// in them.
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std::vector<MachineBasicBlock*> DeadBlocks;
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for (MachineBasicBlock &BB : F) {
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// Test for deadness.
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if (!Reachable.count(&BB)) {
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DeadBlocks.push_back(&BB);
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// Update dominator and loop info.
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if (MLI) MLI->removeBlock(&BB);
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if (MDT && MDT->getNode(&BB)) MDT->eraseNode(&BB);
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if (MPDT && MPDT->getNode(&BB))
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MPDT->eraseNode(&BB);
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while (!BB.succ_empty()) {
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(*BB.succ_begin())->removePHIsIncomingValuesForPredecessor(BB);
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BB.removeSuccessor(BB.succ_begin());
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}
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}
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}
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// Actually remove the blocks now.
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for (MachineBasicBlock *BB : DeadBlocks) {
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// Remove any call information for calls in the block.
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for (auto &I : BB->instrs())
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if (I.shouldUpdateAdditionalCallInfo())
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BB->getParent()->eraseAdditionalCallInfo(&I);
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BB->eraseFromParent();
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}
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// Cleanup PHI nodes.
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for (MachineBasicBlock &BB : F) {
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// Prune unneeded PHI entries.
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SmallPtrSet<MachineBasicBlock *, 8> preds(llvm::from_range,
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BB.predecessors());
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for (MachineInstr &Phi : make_early_inc_range(BB.phis())) {
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for (unsigned i = Phi.getNumOperands() - 1; i >= 2; i -= 2) {
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if (!preds.count(Phi.getOperand(i).getMBB())) {
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Phi.removeOperand(i);
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Phi.removeOperand(i - 1);
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ModifiedPHI = true;
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}
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}
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if (Phi.getNumOperands() == 3) {
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const MachineOperand &Input = Phi.getOperand(1);
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const MachineOperand &Output = Phi.getOperand(0);
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Register InputReg = Input.getReg();
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Register OutputReg = Output.getReg();
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assert(Output.getSubReg() == 0 && "Cannot have output subregister");
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ModifiedPHI = true;
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if (InputReg != OutputReg) {
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MachineRegisterInfo &MRI = F.getRegInfo();
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unsigned InputSub = Input.getSubReg();
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if (InputSub == 0 &&
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MRI.constrainRegClass(InputReg, MRI.getRegClass(OutputReg)) &&
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!Input.isUndef()) {
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MRI.replaceRegWith(OutputReg, InputReg);
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} else {
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// The input register to the PHI has a subregister or it can't be
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// constrained to the proper register class or it is undef:
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// insert a COPY instead of simply replacing the output
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// with the input.
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const TargetInstrInfo *TII = F.getSubtarget().getInstrInfo();
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BuildMI(BB, BB.getFirstNonPHI(), Phi.getDebugLoc(),
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TII->get(TargetOpcode::COPY), OutputReg)
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.addReg(InputReg, getRegState(Input), InputSub);
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}
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Phi.eraseFromParent();
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}
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}
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}
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}
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F.RenumberBlocks();
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if (MDT)
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MDT->updateBlockNumbers();
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if (MPDT)
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MPDT->updateBlockNumbers();
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return (!DeadBlocks.empty() || ModifiedPHI);
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}
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