Thomas Lively 82a13d05ab [WebAssembly] Update relaxed SIMD opcodes and names ...

to reflect the latest state of the proposal:
https://github.com/WebAssembly/relaxed-simd/blob/main/proposals/relaxed-simd/Overview.md#binary-format.
Moves code around to match the instruction order from the proposal, but the only
functional changes are to the names and opcodes.

Reviewed By: aheejin

Differential Revision: https://reviews.llvm.org/D125726

2022-05-16 17:51:45 -07:00

..

AArch64

[MC] [Win64EH] Check for matches between epilogs and the prolog on ARM64

2022-05-17 00:41:39 +03:00

AMDGPU

[AMDGPU] Shrink MAD/FMA to MADAK/MADMK/FMAAK/FMAMK on GFX10

2022-05-16 15:15:23 +01:00

ARC

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ARM

[AArch64][ARM][RISCV][X86] Add test cases for PR55484. NFC

2022-05-16 09:28:11 -07:00

AVR

[AVR] Always expand STDSPQRr & STDWSPQRr

2022-05-05 03:10:59 +00:00

BPF

[BPF] Implement mod operation

2022-05-12 10:59:18 +08:00

CSKY

[CSKY] support select instruction in floating type

2022-04-08 12:38:50 +08:00

DirectX

[DirectX backend] Add pass to emit dxil metadata.

2022-05-11 08:40:13 -07:00

Generic

[NVPTX][tests] add "XFAIL: nvptx" for some tests

2022-04-26 17:26:56 +03:00

Hexagon

[NFC] Rename Instrinsic to Intrinsic

2022-04-25 18:13:23 +01:00

Inputs

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Lanai

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LoongArch

[LoongArch] Add support for selecting constant materializations.

2022-04-15 12:04:35 +08:00

M68k

[M68k] Regenerate cmp.ll tests

2022-04-21 16:54:00 +01:00

Mips

[DAG] Enable ISD::SHL SimplifyMultipleUseDemandedBits handling inside SimplifyDemandedBits

2022-05-14 09:50:01 +01:00

MIR

[X86] Check the address in machine verifier

2022-04-28 10:05:39 +08:00

MLRegalloc

[mlgo] Fix test

2022-05-11 10:07:40 -07:00

MSP430

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NVPTX

[NVPTX] Prefix "$L__" for branch label names

2022-04-30 21:55:20 +02:00

PowerPC

[TargetLowering] Expand the last stage of i16 popcnt using shift+add+and instead of mul+shift.

2022-05-16 09:27:44 -07:00

RISCV

[RISCV] Use classic dataflow for VSETVLI insertion

2022-05-16 17:06:27 -07:00

SPARC

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SPIRV

[SPIRV] Add SPIR-V specific intrinsics, two passes and tests

2022-05-06 03:02:00 +03:00

SystemZ

[DAG] Enable ISD::SHL SimplifyMultipleUseDemandedBits handling inside SimplifyDemandedBits

2022-05-14 09:50:01 +01:00

Thumb

[AArch64][ARM][RISCV][X86] Add test cases for PR55484. NFC

2022-05-16 09:28:11 -07:00

Thumb2

[DAG] Enable ISD::SHL SimplifyMultipleUseDemandedBits handling inside SimplifyDemandedBits

2022-05-14 09:50:01 +01:00

VE

Revert "[CodeGen] Place SDNode debug ID declaration under appropriate #if"

2022-04-06 20:32:53 +03:00

WebAssembly

[WebAssembly] Update relaxed SIMD opcodes and names

2022-05-16 17:51:45 -07:00

WinCFGuard

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WinEH

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X86

[AArch64][ARM][RISCV][X86] Add test cases for PR55484. NFC

2022-05-16 09:28:11 -07:00

XCore

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