f83ab2b3be
Currently when a stack access is out of range of an sp-relative ldr or str then we jump straight to generating the offset with a literal pool load or mov32 pseudo-instruction. This patch improves that in two ways: * If the offset is within range of sp-relative add plus an ldr then use that. * When we use the mov32 pseudo-instruction, if putting part of the offset into the ldr will simplify the expansion of the mov32 then do so. Differential Revision: https://reviews.llvm.org/D156875
52 lines
1.7 KiB
LLVM
52 lines
1.7 KiB
LLVM
; RUN: llc -mtriple=arm-eabi %s -o /dev/null
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; RUN: llc -mtriple=thumbv6m-eabi -mattr=+execute-only %s -o - -filetype=obj | \
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; RUN: llvm-objdump -d --no-leading-addr --no-show-raw-insn - | FileCheck %s
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define void @test1() {
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; CHECK-LABEL: <test1>:
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;; are we using correct prologue immediate materialization pattern for
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;; execute only
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; CHECK: sub sp, #0x100
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%tmp = alloca [ 64 x i32 ] , align 4
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ret void
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}
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define void @test2() {
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; CHECK-LABEL: <test2>:
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;; are we using correct prologue immediate materialization pattern for
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;; execute-only
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; CHECK: movs [[REG:r[0-9]+]], #0xff
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; CHECK-NEXT: lsls [[REG]], [[REG]], #0x8
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; CHECK-NEXT: adds [[REG]], #0xff
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; CHECK-NEXT: lsls [[REG]], [[REG]], #0x8
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; CHECK-NEXT: adds [[REG]], #0xef
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; CHECK-NEXT: lsls [[REG]], [[REG]], #0x8
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; CHECK-NEXT: adds [[REG]], #0xb8
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%tmp = alloca [ 4168 x i8 ] , align 4
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ret void
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}
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define i32 @test3() {
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;; are we using correct prologue immediate materialization pattern for
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;; execute-only
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; CHECK-LABEL: <test3>:
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; CHECK: movs [[REG:r[0-9]+]], #0xcf
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; CHECK-NEXT: lsls [[REG]], [[REG]], #0x8
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; CHECK-NEXT: adds [[REG]], #0xff
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; CHECK-NEXT: lsls [[REG]], [[REG]], #0x8
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; CHECK-NEXT: adds [[REG]], #0xff
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; CHECK-NEXT: lsls [[REG]], [[REG]], #0x8
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; CHECK-NEXT: adds [[REG]], #0xf0
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%retval = alloca i32, align 4
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%tmp = alloca i32, align 4
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%a = alloca [u0x30000001 x i8], align 16
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store i32 0, ptr %tmp
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;; are we choosing correct store/tSTRspi pattern for execute-only
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; CHECK: movs [[REG:r[0-9]+]], #0x30
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; CHECK-NEXT: lsls [[REG]], [[REG]], #0x18
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; CHECK-NEXT: add [[REG]], sp
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; CHECK-NEXT: str {{r[0-9]+}}, [[[REG]], #0x8]
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%tmp1 = load i32, ptr %tmp
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ret i32 %tmp1
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}
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