llvm-project

AsmParser

[RISCV] Enable framework to resolve encoding conflicts among vendor-specific CSRs (#97287 )

2024-07-11 20:12:17 -07:00

Disassembler

[RISCV] Add QingKe "XW" compressed opcode extension (#97925 )

2024-07-11 11:10:02 +08:00

GISel

[GISel] Make create.*InstructionSelector arguments const (#98243 )

2024-07-10 09:01:27 -04:00

MCA

[RISCV][NFC] Include RISCVVInversePseudosTable in RISCVMCTargetDesc

2024-04-24 09:29:20 -07:00

MCTargetDesc

[RISCV] Create mapping symbols with non-unique names

2024-07-22 23:07:27 -07:00

TargetInfo

…

CMakeLists.txt

[RISCV] Convert AVLs with vlenb to VLMAX where possible (#97800 )

2024-07-11 14:22:00 +08:00

RISCV.h

[RISCV] Convert AVLs with vlenb to VLMAX where possible (#97800 )

2024-07-11 14:22:00 +08:00

RISCV.td

[RISCV] Add scheduling model for Syntacore SCR3 (#95427 )

2024-06-25 11:34:59 +03:00

RISCVAsmPrinter.cpp

[IR] Don't include Module.h in Analysis.h (NFC) (#97023 )

2024-06-28 14:30:47 +02:00

RISCVCallingConv.td

[RISCV] RISCV vector calling convention (1/2) (#77560 )

2024-03-27 23:03:13 +08:00

RISCVCodeGenPrepare.cpp

[RISCV][NFC] Fix intrinsic misspelled in a comment (#98998 )

2024-07-17 07:07:33 +02:00

RISCVCombine.td

…

RISCVDeadRegisterDefinitions.cpp

[CodeGen][NewPM] Port LiveIntervals to new pass manager (#98118 )

2024-07-10 19:34:48 +08:00

RISCVExpandAtomicPseudoInsts.cpp

…

RISCVExpandPseudoInsts.cpp

[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954 )

2024-04-16 15:40:32 -07:00

RISCVFeatures.td

[RISCV] Mark zacas as experimental again due to unresolved ABI issue (#99898 )

2024-07-23 08:06:15 +01:00

RISCVFrameLowering.cpp

[RISCV] Remove getOffsetOfLocalArea() (#93765 )

2024-06-17 15:38:37 +08:00

RISCVFrameLowering.h

[RISCV] Add CFI information for vector callee-saved registers (#86811 )

2024-04-17 10:42:40 +08:00

RISCVGatherScatterLowering.cpp

[RISCV] Emit VP strided loads/stores in RISCVGatherScatterLowering (#98111 )

2024-07-24 13:56:22 +08:00

RISCVGISel.td

[RISCV][GISel] Support G_ROTL/G_ROTR with Zbb. (#72825 )

2023-12-04 13:00:34 -08:00

RISCVInsertReadWriteCSR.cpp

[CodeGen] Make the parameter TRI required in some functions. (#85968 )

2024-04-24 14:24:14 +01:00

RISCVInsertVSETVLI.cpp

[RISCV] Reverse iteration/deletion structure in vsetvli coalescing [NFC] (#98936 )

2024-07-23 08:52:04 -07:00

RISCVInsertWriteVXRM.cpp

[CodeGen] Make the parameter TRI required in some functions. (#85968 )

2024-04-24 14:24:14 +01:00

RISCVInstrFormats.td

[RISCV] Rename OP-P to OP-VE. (#87546 )

2024-04-05 17:02:03 -07:00

RISCVInstrFormatsC.td

…

RISCVInstrFormatsV.td

…

RISCVInstrGISel.td

[RISCV][GISEL] Legalize G_ZEXT, G_SEXT, and G_ANYEXT, G_SPLAT_VECTOR, and G_ICMP for scalable vector types

2024-04-03 15:27:15 -07:00

RISCVInstrInfo.cpp

MachineOutliner: Use PM to query MachineModuleInfo (#99688 )

2024-07-24 13:22:56 +04:00

RISCVInstrInfo.h

MachineOutliner: Use PM to query MachineModuleInfo (#99688 )

2024-07-24 13:22:56 +04:00

RISCVInstrInfo.td

[RISCV] Add QingKe "XW" compressed opcode extension (#97925 )

2024-07-11 11:10:02 +08:00

RISCVInstrInfoA.td

DAG: Replace bitwidth with type in suffix in atomic tablegen ops (#94845 )

2024-06-13 11:52:22 +02:00

RISCVInstrInfoC.td

[RISCV] Fix InsnCI register type (#100113 )

2024-07-23 21:19:57 +08:00

RISCVInstrInfoD.td

Revert "Intrinsic: introduce minimumnum and maximumnum (#93841 )"

2024-06-21 08:34:04 +02:00

RISCVInstrInfoF.td

Revert "Intrinsic: introduce minimumnum and maximumnum (#93841 )"

2024-06-21 08:34:04 +02:00

RISCVInstrInfoM.td

[RISCV] Make M imply Zmmul (#95070 )

2024-06-21 11:11:10 +08:00

RISCVInstrInfoSFB.td

[RISCV][NFC] Move SFB pseudos and patterns to RISCVInstrInfoSFB.td (#80945 )

2024-02-07 16:03:30 +08:00

RISCVInstrInfoV.td

[RISCV] Split sched classes for vrgather.vv and vrgatherei16.vv (#92768 )

2024-05-23 12:10:46 -04:00

RISCVInstrInfoVPseudos.td

[RISCV] Don't fold vmerge.vvm or vmv.v.v into vredsum.vs if AVL changed (#99006 )

2024-07-17 12:50:17 +08:00

RISCVInstrInfoVSDPatterns.td

[RISCV] Add unit strided load/store to whole register peephole (#100116 )

2024-07-24 11:52:54 +08:00

RISCVInstrInfoVVLPatterns.td

[RISCV] Replace VNCLIP RISCVISD opcodes with TRUNCATE_VECTOR_VL_SSAT/USAT opcodes (#100173 )

2024-07-23 14:57:31 -07:00

RISCVInstrInfoXCV.td

[RISCV] Implement Intrinsics for XCVmac Extension in CV32E40P (#83112 )

2024-07-15 10:25:25 +10:00

RISCVInstrInfoXSf.td

[RISCV] Add scheduling information for SiFive VCIX (#86093 )

2024-04-16 13:55:45 +08:00

RISCVInstrInfoXTHead.td

[RISCV] Move strength reduction of mul X, 3/5/9*2^N to combine (#89966 )

2024-05-08 10:13:01 -07:00

RISCVInstrInfoXVentana.td

…

RISCVInstrInfoXwch.td

[RISCV] Add QingKe "XW" compressed opcode extension (#97925 )

2024-07-11 11:10:02 +08:00

RISCVInstrInfoZa.td

DAG: Replace bitwidth with type in suffix in atomic tablegen ops (#94845 )

2024-06-13 11:52:22 +02:00

RISCVInstrInfoZalasr.td

[RISCV][MC] MC layer support for the experimental zalasr extension (#79911 )

2024-02-01 10:58:21 -08:00

RISCVInstrInfoZb.td

[RISCV] Rework zext.h handling for Zbkb again. (#96957 )

2024-06-27 21:35:33 -07:00

RISCVInstrInfoZc.td

[RISCV] Make M imply Zmmul (#95070 )

2024-06-21 11:11:10 +08:00

RISCVInstrInfoZcmop.td

[RISCV] Correct the spelling of the Zcmop mnemonics. (#88826 )

2024-04-15 22:33:14 -07:00

RISCVInstrInfoZfa.td

[RISCV] Apply IsSignExtendingOpW = 1 on fcvtmod.w.d (#69633 )

2023-10-19 14:55:33 -07:00

RISCVInstrInfoZfbfmin.td

[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357 )

2023-11-01 09:36:41 -07:00

RISCVInstrInfoZfh.td

[RISCV] Add casts to isel patterns that produce more than 1 instruction.

2024-02-08 23:38:19 -08:00

RISCVInstrInfoZicbo.td

[RISCV] Match prefetch address with offset (#66072 )

2023-10-20 14:22:48 +08:00

RISCVInstrInfoZicfiss.td

[RISCV] Add MC layer support for Zicfiss. (#66043 )

2023-12-30 15:40:20 +08:00

RISCVInstrInfoZicond.td

[RISCV] Graduate Zicond to non-experimental (#79811 )

2024-01-29 15:58:54 +00:00

RISCVInstrInfoZimop.td

[RISCV] Zimop/Zcmop are ratified

2024-04-08 16:40:02 +08:00

RISCVInstrInfoZk.td

[RISCV][NFC] Add base classes of Operand and uimm/simm (#68472 )

2023-10-08 14:13:08 +08:00

RISCVInstrInfoZvfbf.td

…

RISCVInstrInfoZvk.td

[RISCV] Remove unused defaults for sew paramters in tablegen. NFC

2024-06-07 23:15:53 -07:00

RISCVISelDAGToDAG.cpp

[RISCV] Don't fold vmerge.vvm or vmv.v.v into vredsum.vs if AVL changed (#99006 )

2024-07-17 12:50:17 +08:00

RISCVISelDAGToDAG.h

[RISCV] Codegen support for XCVmem extension (#76916 )

2024-06-07 21:45:49 +08:00

RISCVISelLowering.cpp

[RISCV] Emit VP strided loads/stores in RISCVGatherScatterLowering (#98111 )

2024-07-24 13:56:22 +08:00

RISCVISelLowering.h

[RISCV] Replace VNCLIP RISCVISD opcodes with TRUNCATE_VECTOR_VL_SSAT/USAT opcodes (#100173 )

2024-07-23 14:57:31 -07:00

RISCVMachineFunctionInfo.cpp

…

RISCVMachineFunctionInfo.h

[llvm-project] Fix typo "seperate" (#95373 )

2024-06-13 20:20:27 +01:00

RISCVMacroFusion.td

[RISCV] Use TableGen-based macro fusion (#72224 )

2024-01-25 17:10:49 +08:00

RISCVMakeCompressible.cpp

[RISCV] Teach RISCVMakeCompressible handle byte/half load/store for Zcb. (#83375 )

2024-03-27 13:40:38 +08:00

RISCVMergeBaseOffset.cpp

[RISCV] Add a rematerializable pseudo instruction for LUI+ADDI for global addresses. (#93352 )

2024-05-28 15:05:23 -07:00

RISCVMoveMerger.cpp

[RISCV] Cleanup pass initialization.

2023-12-07 18:21:38 -08:00

RISCVOptWInstrs.cpp

[CodeGen] Make the parameter TRI required in some functions. (#85968 )

2024-04-24 14:24:14 +01:00

RISCVPostRAExpandPseudoInsts.cpp

[RISCV] Remove unneeded code from RISCVPostRAExpandPseudo::expandMovImm. NFC

2024-06-27 18:42:27 -07:00

RISCVProcessors.td

[RISCV] Reverse default assumption about performance of vlseN.v vd, (rs1), x0 (#98205 )

2024-07-10 07:35:56 -07:00

RISCVProfiles.td

[RISCV] Gate unratified profiles behind -menable-experimental-extensions (#92167 )

2024-05-15 21:09:43 +01:00

RISCVPushPopOptimizer.cpp

[RISCV] Add correct Uses, Defs, isReturn to Zcmp (#81039 )

2024-02-07 14:30:45 -08:00

RISCVRedundantCopyElimination.cpp

[RISCV] Codegen support for XCVbi extension (#89719 )

2024-05-08 11:22:16 +08:00

RISCVRegisterInfo.cpp

[RISCV] Mark all registers marked isConstant as reserved (#96002 )

2024-06-23 15:44:41 -07:00

RISCVRegisterInfo.h

[RISCV] Store VLMul/NF into RegisterClass's TSFlags

2024-04-08 13:35:37 +08:00

RISCVRegisterInfo.td

[RISCV] Use software guarded branch for indirect jump table branch. (#66762 )

2024-05-14 14:44:25 +08:00

RISCVSchedRocket.td

[RISCV] Add Sched classes for vector crypto instructions (#90068 )

2024-05-03 11:11:29 -04:00

RISCVSchedSiFive7.td

[RISCV] Do not check PostRAScheduler in enablePostRAScheduler (#92781 )

2024-05-24 14:31:14 -04:00

RISCVSchedSiFiveP400.td

[RISCV] Adjust FP load latencies from 6 to 5 in SiFiveP400/P600 scheduling models (#93735 )

2024-05-30 08:47:27 -07:00

RISCVSchedSiFiveP600.td

[RISCV] Adjust FP load latencies from 6 to 5 in SiFiveP400/P600 scheduling models (#93735 )

2024-05-30 08:47:27 -07:00

RISCVSchedSyntacoreSCR1.td

[RISCV][NFC] Cleanup SCR1 sched model (#96088 )

2024-06-20 18:14:09 +03:00

RISCVSchedSyntacoreSCR3.td

[RISCV] Add scheduling model for Syntacore SCR3 (#95427 )

2024-06-25 11:34:59 +03:00

RISCVSchedule.td

[RISCV][NFC] Add UnsupportedSched<F|D|A> multiclasses (#95948 )

2024-06-19 12:37:47 +03:00

RISCVScheduleV.td

[RISCV] Split sched classes for vrgather.vv and vrgatherei16.vv (#92768 )

2024-05-23 12:10:46 -04:00

RISCVScheduleXSf.td

[RISCV] Add scheduling information for SiFive VCIX (#86093 )

2024-04-16 13:55:45 +08:00

RISCVScheduleZb.td

[RISCV] Add sched classes for Zbb integer min max instructions

2024-03-14 06:02:42 -07:00

RISCVScheduleZvk.td

[RISCV] Add Sched classes for vector crypto instructions (#90068 )

2024-05-03 11:11:29 -04:00

RISCVSchedXiangShanNanHu.td

[RISCV] Add Sched classes for vector crypto instructions (#90068 )

2024-05-03 11:11:29 -04:00

RISCVSubtarget.cpp

[RISCV] Store a std::unique_ptr<RISCVRegisterBankInfo> in RISCVSubtarget. NFC (#98375 )

2024-07-10 14:17:56 -07:00

RISCVSubtarget.h

[RISCV] Store a std::unique_ptr<RISCVRegisterBankInfo> in RISCVSubtarget. NFC (#98375 )

2024-07-10 14:17:56 -07:00

RISCVSystemOperands.td

[RISCV] Enable framework to resolve encoding conflicts among vendor-specific CSRs (#97287 )

2024-07-11 20:12:17 -07:00

RISCVTargetMachine.cpp

[CodeGen] change prototype of regalloc filter function (#93525 )

2024-07-22 16:49:39 +05:30

RISCVTargetMachine.h

[RISCV][LoopIdiomVectorize] Support VP intrinsics in LoopIdiomVectorize (#94082 )

2024-07-02 18:48:28 -07:00

RISCVTargetObjectFile.cpp

[IR] Don't include Module.h in Analysis.h (NFC) (#97023 )

2024-06-28 14:30:47 +02:00

RISCVTargetObjectFile.h

[RISCV] Place mergeable small read only data into srodata section (#82214 )

2024-03-11 13:57:06 +08:00

RISCVTargetTransformInfo.cpp

[RISCV] Don't cost vector arithmetic fp ops as cheaper than scalar (#99594 )

2024-07-22 13:56:10 +08:00

RISCVTargetTransformInfo.h

Revert "[RISCV] Enable TTI::shouldDropLSRSolutionIfLessProfitable by default" (#98328 )

2024-07-10 15:33:20 +01:00

RISCVVectorPeephole.cpp

[RISCV] Add unit strided load/store to whole register peephole (#100116 )

2024-07-24 11:52:54 +08:00