e09032f7a3
The existing StackFrameLayoutAnalysis details do not do well with Scalable vector stack slots, which are not marked as scalable and intertwined with the other fixed-size slots. This patch adds some very basic support, marking them as scalable and sorting them to the end of the list. The slot addresses are not really correct (for fixed as well as scalable), but this prints something a little better with the limited information curently available.
136 lines
5.8 KiB
LLVM
136 lines
5.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=aarch64 -mattr=+sve2 | FileCheck %s --check-prefixes=CHECK
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; RUN: llc < %s -mtriple=aarch64 -mattr=+sve2 -pass-remarks-analysis=stack-frame-layout 2>&1 >/dev/null | FileCheck %s --check-prefixes=CHECK-FRAMELAYOUT
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; CHECK-FRAMELAYOUT-LABEL: Function: csr_d8_allocnxv4i32i32f64
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; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-8], Type: Spill, Align: 8, Size: 8
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; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16], Type: Spill, Align: 8, Size: 8
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; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-20], Type: Variable, Align: 4, Size: 4
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; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-32], Type: Variable, Align: 8, Size: 8
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; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16], Type: Variable, Align: 16, Size: vscale x 16
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define i32 @csr_d8_allocnxv4i32i32f64(double %d) "aarch64_pstate_sm_compatible" {
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; CHECK-LABEL: csr_d8_allocnxv4i32i32f64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: str x29, [sp, #8] // 8-byte Folded Spill
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x20, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 32 + 8 * VG
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; CHECK-NEXT: .cfi_offset w29, -8
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; CHECK-NEXT: .cfi_offset b8, -16
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; CHECK-NEXT: mov z1.s, #0 // =0x0
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: add x8, sp, #16
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: //APP
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; CHECK-NEXT: //NO_APP
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; CHECK-NEXT: str wzr, [sp, #12]
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; CHECK-NEXT: str d0, [sp]
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; CHECK-NEXT: st1w { z1.s }, p0, [x8]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ldr x29, [sp, #8] // 8-byte Folded Reload
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; CHECK-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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entry:
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%a = alloca <vscale x 4 x i32>
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%b = alloca i32
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%c = alloca double
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tail call void asm sideeffect "", "~{d8}"() #1
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store <vscale x 4 x i32> zeroinitializer, ptr %a
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store i32 zeroinitializer, ptr %b
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store double %d, ptr %c
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ret i32 0
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}
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; CHECK-FRAMELAYOUT-LABEL: Function: csr_d8_allocnxv4i32i32f64_fp
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; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-8], Type: Spill, Align: 8, Size: 8
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; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16], Type: Spill, Align: 8, Size: 8
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; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-20], Type: Variable, Align: 4, Size: 4
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; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-32], Type: Spill, Align: 16, Size: 8
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; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-40], Type: Variable, Align: 8, Size: 8
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; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16], Type: Variable, Align: 16, Size: vscale x 16
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define i32 @csr_d8_allocnxv4i32i32f64_fp(double %d) "aarch64_pstate_sm_compatible" "frame-pointer"="all" {
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; CHECK-LABEL: csr_d8_allocnxv4i32i32f64_fp:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
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; CHECK-NEXT: stp x29, x30, [sp, #16] // 16-byte Folded Spill
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; CHECK-NEXT: add x29, sp, #16
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: .cfi_def_cfa w29, 16
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; CHECK-NEXT: .cfi_offset w30, -8
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; CHECK-NEXT: .cfi_offset w29, -16
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; CHECK-NEXT: .cfi_offset b8, -32
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; CHECK-NEXT: mov z1.s, #0 // =0x0
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: addvl x8, sp, #1
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; CHECK-NEXT: //APP
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; CHECK-NEXT: //NO_APP
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; CHECK-NEXT: str wzr, [x8, #28]
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; CHECK-NEXT: sub x8, x29, #16
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: str d0, [sp, #8]
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; CHECK-NEXT: st1w { z1.s }, p0, [x8, #-1, mul vl]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ldp x29, x30, [sp, #16] // 16-byte Folded Reload
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; CHECK-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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entry:
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%a = alloca <vscale x 4 x i32>
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%b = alloca i32
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%c = alloca double
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tail call void asm sideeffect "", "~{d8}"() #1
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store <vscale x 4 x i32> zeroinitializer, ptr %a
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store i32 zeroinitializer, ptr %b
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store double %d, ptr %c
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ret i32 0
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}
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; CHECK-FRAMELAYOUT-LABEL: Function: svecc_z8_allocnxv4i32i32f64_fp
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; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-8], Type: Spill, Align: 8, Size: 8
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; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16], Type: Spill, Align: 8, Size: 8
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; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-20], Type: Variable, Align: 4, Size: 4
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; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-32], Type: Variable, Align: 8, Size: 8
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; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16], Type: Spill, Align: 16, Size: vscale x 16
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; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-32], Type: Variable, Align: 16, Size: vscale x 16
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define i32 @svecc_z8_allocnxv4i32i32f64_fp(double %d, <vscale x 4 x i32> %v) "aarch64_pstate_sm_compatible" "frame-pointer"="all" {
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; CHECK-LABEL: svecc_z8_allocnxv4i32i32f64_fp:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
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; CHECK-NEXT: mov x29, sp
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: str z8, [sp] // 16-byte Folded Spill
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: .cfi_def_cfa w29, 16
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; CHECK-NEXT: .cfi_offset w30, -8
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; CHECK-NEXT: .cfi_offset w29, -16
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; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x78, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d8 @ cfa - 16 - 8 * VG
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: //APP
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; CHECK-NEXT: //NO_APP
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; CHECK-NEXT: str wzr, [sp, #12]
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; CHECK-NEXT: st1w { z1.s }, p0, [x29, #-2, mul vl]
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; CHECK-NEXT: str d0, [sp], #16
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr z8, [sp] // 16-byte Folded Reload
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
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; CHECK-NEXT: ret
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entry:
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%a = alloca <vscale x 4 x i32>
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%b = alloca i32
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%c = alloca double
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tail call void asm sideeffect "", "~{d8}"() #1
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store <vscale x 4 x i32> %v, ptr %a
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store i32 zeroinitializer, ptr %b
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store double %d, ptr %c
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ret i32 0
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}
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