571b787b83
NVPTX, SPIRV, and WebAssembly pass virtual registers to this function since they don't perform register allocation. We need to use Register to avoid a virtual register being converted to MCRegister by the caller.
120 lines
4.7 KiB
C++
120 lines
4.7 KiB
C++
//=- LoongArchInstrInfo.h - LoongArch Instruction Information ---*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the LoongArch implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H
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#define LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H
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#include "LoongArchRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "LoongArchGenInstrInfo.inc"
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namespace llvm {
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class LoongArchSubtarget;
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class LoongArchInstrInfo : public LoongArchGenInstrInfo {
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public:
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explicit LoongArchInstrInfo(LoongArchSubtarget &STI);
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MCInst getNop() const override;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, Register DstReg, Register SrcReg,
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bool KillSrc, bool RenamableDest = false,
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bool RenamableSrc = false) const override;
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void storeRegToStackSlot(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
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bool IsKill, int FrameIndex, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI, Register VReg,
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MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
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void loadRegFromStackSlot(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg,
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int FrameIndex, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI, Register VReg,
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MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
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// Materializes the given integer Val into DstReg.
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void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, Register DstReg, uint64_t Val,
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MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const;
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unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
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bool isAsCheapAsAMove(const MachineInstr &MI) const override;
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MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const override;
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bool isBranchOffsetInRange(unsigned BranchOpc,
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int64_t BrOffset) const override;
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bool isSchedulingBoundary(const MachineInstr &MI,
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const MachineBasicBlock *MBB,
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const MachineFunction &MF) const override;
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved = nullptr) const override;
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &dl,
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int *BytesAdded = nullptr) const override;
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void insertIndirectBranch(MachineBasicBlock &MBB,
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MachineBasicBlock &NewDestBB,
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MachineBasicBlock &RestoreBB, const DebugLoc &DL,
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int64_t BrOffset, RegScavenger *RS) const override;
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bool
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reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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std::pair<unsigned, unsigned>
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decomposeMachineOperandsTargetFlags(unsigned TF) const override;
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ArrayRef<std::pair<unsigned, const char *>>
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getSerializableDirectMachineOperandTargetFlags() const override;
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ArrayRef<std::pair<unsigned, const char *>>
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getSerializableBitmaskMachineOperandTargetFlags() const override;
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protected:
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const LoongArchSubtarget &STI;
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};
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namespace LoongArch {
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// Returns true if this is the sext.w pattern, addi.w rd, rs, 0.
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bool isSEXT_W(const MachineInstr &MI);
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// Mask assignments for floating-point.
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static constexpr unsigned FClassMaskSignalingNaN = 0x001;
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static constexpr unsigned FClassMaskQuietNaN = 0x002;
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static constexpr unsigned FClassMaskNegativeInfinity = 0x004;
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static constexpr unsigned FClassMaskNegativeNormal = 0x008;
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static constexpr unsigned FClassMaskNegativeSubnormal = 0x010;
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static constexpr unsigned FClassMaskNegativeZero = 0x020;
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static constexpr unsigned FClassMaskPositiveInfinity = 0x040;
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static constexpr unsigned FClassMaskPositiveNormal = 0x080;
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static constexpr unsigned FClassMaskPositiveSubnormal = 0x100;
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static constexpr unsigned FClassMaskPositiveZero = 0x200;
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} // namespace LoongArch
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H
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