160 lines
6.2 KiB
LLVM
160 lines
6.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -mcpu=gfx1200 < %s | FileCheck --check-prefix=GFX12 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -mcpu=gfx1200 -mattr=+cumode < %s | FileCheck --check-prefix=GFX12 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -mcpu=gfx1250 < %s | FileCheck --check-prefixes=GFX1250 %s
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define amdgpu_kernel void @flat_last_use_load_0(ptr %in, ptr %out) {
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; GFX12-LABEL: flat_last_use_load_0:
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; GFX12: ; %bb.0: ; %entry
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; GFX12-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
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; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_mov_b32_e32 v0, s2
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; GFX12-NEXT: v_mov_b32_e32 v1, s3
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; GFX12-NEXT: flat_load_b32 v2, v[0:1] th:TH_LOAD_LU
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; GFX12-NEXT: v_mov_b32_e32 v0, s0
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; GFX12-NEXT: v_mov_b32_e32 v1, s1
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: flat_store_b32 v[0:1], v2
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; GFX12-NEXT: s_endpgm
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;
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; GFX1250-LABEL: flat_last_use_load_0:
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; GFX1250: ; %bb.0: ; %entry
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; GFX1250-NEXT: v_mov_b32_e32 v0, 0
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; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
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; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
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; GFX1250-NEXT: s_wait_kmcnt 0x0
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; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3] th:TH_LOAD_LU
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; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: s_endpgm
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entry:
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%val = load i32, ptr %in, align 4, !amdgpu.last.use !{}
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store i32 %val, ptr %out
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ret void
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}
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define amdgpu_kernel void @flat_last_use_load_1(ptr %in, ptr %out) {
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; GFX12-LABEL: flat_last_use_load_1:
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; GFX12: ; %bb.0: ; %entry
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; GFX12-NEXT: s_mov_b64 s[0:1], s[4:5]
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; GFX12-NEXT: s_load_b64 s[4:5], s[0:1], 0x0
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; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x8
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; GFX12-NEXT: s_mov_b32 s2, 0x3ff
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; GFX12-NEXT: v_and_b32_e64 v0, v0, s2
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; GFX12-NEXT: s_mov_b32 s2, 2
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; GFX12-NEXT: s_wait_alu 0xfffe
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; GFX12-NEXT: v_lshlrev_b32_e64 v1, s2, v0
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; GFX12-NEXT: s_mov_b32 s2, 0
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; GFX12-NEXT: ; implicit-def: $sgpr2
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; GFX12-NEXT: v_mov_b32_e32 v0, 0
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; GFX12-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec
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; GFX12-NEXT: v_mov_b32_e32 v2, v0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_mov_b32 s3, s4
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; GFX12-NEXT: v_mov_b32_e32 v0, v1
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; GFX12-NEXT: s_mov_b32 s2, s5
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; GFX12-NEXT: v_mov_b32_e32 v1, v2
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; GFX12-NEXT: s_wait_alu 0xfffe
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; GFX12-NEXT: v_add_co_u32 v0, s3, s3, v0
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; GFX12-NEXT: s_wait_alu 0xf1ff
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; GFX12-NEXT: v_add_co_ci_u32_e64 v2, s2, s2, v1, s3
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; GFX12-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec
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; GFX12-NEXT: v_mov_b32_e32 v1, v2
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; GFX12-NEXT: flat_load_b32 v2, v[0:1] th:TH_LOAD_LU
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; GFX12-NEXT: v_mov_b32_e32 v0, s0
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; GFX12-NEXT: v_mov_b32_e32 v1, s1
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: flat_store_b32 v[0:1], v2
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; GFX12-NEXT: s_endpgm
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;
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; GFX1250-LABEL: flat_last_use_load_1:
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; GFX1250: ; %bb.0: ; %entry
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; GFX1250-NEXT: v_mov_b32_e32 v1, v0
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; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
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; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
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; GFX1250-NEXT: v_mov_b32_e32 v0, 0
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; GFX1250-NEXT: s_wait_xcnt 0x0
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; GFX1250-NEXT: s_mov_b32 s4, 0x3ff
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; GFX1250-NEXT: v_and_b32_e64 v1, v1, s4
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; GFX1250-NEXT: s_wait_kmcnt 0x0
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; GFX1250-NEXT: flat_load_b32 v1, v1, s[2:3] scale_offset th:TH_LOAD_LU
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; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: s_endpgm
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%val.gep = getelementptr inbounds i32, ptr %in, i32 %tid
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%val = load i32, ptr %val.gep, align 4, !amdgpu.last.use !{}
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store i32 %val, ptr %out
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ret void
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}
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define amdgpu_kernel void @flat_last_use_and_volatile_load(ptr %in, ptr %out) {
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; GFX12-LABEL: flat_last_use_and_volatile_load:
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; GFX12: ; %bb.0: ; %entry
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; GFX12-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
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; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_mov_b32_e32 v0, s2
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; GFX12-NEXT: v_mov_b32_e32 v1, s3
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; GFX12-NEXT: flat_load_b32 v2, v[0:1] th:TH_LOAD_BYPASS scope:SCOPE_SYS
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_loadcnt 0x0
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; GFX12-NEXT: v_mov_b32_e32 v0, s0
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; GFX12-NEXT: v_mov_b32_e32 v1, s1
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; GFX12-NEXT: s_wait_dscnt 0x0
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; GFX12-NEXT: flat_store_b32 v[0:1], v2
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; GFX12-NEXT: s_endpgm
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;
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; GFX1250-LABEL: flat_last_use_and_volatile_load:
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; GFX1250: ; %bb.0: ; %entry
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; GFX1250-NEXT: v_mov_b32_e32 v0, 0
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; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
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; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
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; GFX1250-NEXT: s_wait_kmcnt 0x0
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; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3] th:TH_LOAD_BYPASS scope:SCOPE_SYS
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; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: s_endpgm
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entry:
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%val = load volatile i32, ptr %in, align 4, !amdgpu.last.use !{}
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store i32 %val, ptr %out
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ret void
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}
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define amdgpu_kernel void @flat_last_use_and_nontemporal_load(ptr %in, ptr %out) {
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; GFX12-LABEL: flat_last_use_and_nontemporal_load:
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; GFX12: ; %bb.0: ; %entry
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; GFX12-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
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; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_mov_b32_e32 v0, s2
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; GFX12-NEXT: v_mov_b32_e32 v1, s3
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; GFX12-NEXT: flat_load_b32 v2, v[0:1] th:TH_LOAD_LU
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; GFX12-NEXT: v_mov_b32_e32 v0, s0
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; GFX12-NEXT: v_mov_b32_e32 v1, s1
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: flat_store_b32 v[0:1], v2
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; GFX12-NEXT: s_endpgm
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;
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; GFX1250-LABEL: flat_last_use_and_nontemporal_load:
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; GFX1250: ; %bb.0: ; %entry
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; GFX1250-NEXT: v_mov_b32_e32 v0, 0
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; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
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; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
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; GFX1250-NEXT: s_wait_kmcnt 0x0
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; GFX1250-NEXT: flat_load_b32 v1, v0, s[2:3] th:TH_LOAD_LU
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; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-NEXT: flat_store_b32 v0, v1, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: s_endpgm
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entry:
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%val = load i32, ptr %in, align 4, !amdgpu.last.use !{}, !nontemporal !0
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store i32 %val, ptr %out
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ret void
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}
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!0 = !{i32 1}
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declare i32 @llvm.amdgcn.workitem.id.x()
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