Philip Reames d4545e6fa0 Revert "[RISCV] Enable strict assertions in InsertVSETVLI data flow"
This reverts commit 79a66ec97b4fb8cbc4e0a81ead356caf5507a6ea.

The stronger asserts served their purpose; I stumbled across another bug.  Will reapply once this one is also fixed.

The bug appears to be a variant of a previous one:
* We mutate an instruction in one block.
* That mutation changes the phase3 results of another block.

This is very similiar to a previous issue, except cross block instead of within a single block.
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