d41a73aa94
Support for the unratified 1.0-rc3 specification was introduced in
D133443. The specification has since been ratified (in November 2022
according to the recently ratified extensions list
<https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions>.
A review of the diff
<https://github.com/riscv/riscv-zawrs/compare/V1.0-rc3...main> of the
1.0-rc3 spec vs the current/ratified document shows no changes to the
instruction encoding or naming. At one point, a note was added
<e84f42406a>
indicating Zawrs depends on the Zalrsc extension (not officially
specified, but I believe to be just the LR/SC instructions from the A
extension). The final text ended up as "The instructions in the Zawrs
extension are only useful in conjunction with the LR instructions, which
are provided by the A extension, and which we also expect to be provided
by a narrower Zalrsc extension in the future." I think it's consistent
with this phrasing to not require the A extension for Zawrs, which
matches what was implemented.
No intrinsics are implemented for Zawrs currently, meaning we don't need
to additionally review whether those intrinsics can be considered
finalised and ready for exposure to end users.
Differential Revision: https://reviews.llvm.org/D143507
607 lines
30 KiB
TableGen
607 lines
30 KiB
TableGen
//===-- RISCVFeatures.td - RISCV Features and Extensions ---*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// RISC-V subtarget features and instruction predicates.
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//===----------------------------------------------------------------------===//
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def FeatureStdExtM
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: SubtargetFeature<"m", "HasStdExtM", "true",
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"'M' (Integer Multiplication and Division)">;
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def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
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AssemblerPredicate<(all_of FeatureStdExtM),
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"'M' (Integer Multiplication and Division)">;
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def FeatureStdExtZmmul
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: SubtargetFeature<"zmmul", "HasStdExtZmmul", "true",
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"'Zmmul' (Integer Multiplication)">;
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def HasStdExtMOrZmmul
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: Predicate<"Subtarget->hasStdExtM() || Subtarget->hasStdExtZmmul()">,
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AssemblerPredicate<(any_of FeatureStdExtM, FeatureStdExtZmmul),
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"'M' (Integer Multiplication and Division) or "
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"'Zmmul' (Integer Multiplication)">;
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def FeatureStdExtA
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: SubtargetFeature<"a", "HasStdExtA", "true",
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"'A' (Atomic Instructions)">;
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def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
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AssemblerPredicate<(all_of FeatureStdExtA),
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"'A' (Atomic Instructions)">;
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def FeatureStdExtF
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: SubtargetFeature<"f", "HasStdExtF", "true",
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"'F' (Single-Precision Floating-Point)">;
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def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
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AssemblerPredicate<(all_of FeatureStdExtF),
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"'F' (Single-Precision Floating-Point)">;
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def FeatureStdExtD
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: SubtargetFeature<"d", "HasStdExtD", "true",
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"'D' (Double-Precision Floating-Point)",
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[FeatureStdExtF]>;
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def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
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AssemblerPredicate<(all_of FeatureStdExtD),
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"'D' (Double-Precision Floating-Point)">;
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def FeatureStdExtH
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: SubtargetFeature<"h", "HasStdExtH", "true",
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"'H' (Hypervisor)">;
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def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">,
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AssemblerPredicate<(all_of FeatureStdExtH),
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"'H' (Hypervisor)">;
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def FeatureStdExtZihintpause
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: SubtargetFeature<"zihintpause", "HasStdExtZihintpause", "true",
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"'zihintpause' (Pause Hint)">;
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def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
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AssemblerPredicate<(all_of FeatureStdExtZihintpause),
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"'Zihintpause' (Pause Hint)">;
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def FeatureStdExtZihintntl
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: SubtargetFeature<"experimental-zihintntl", "HasStdExtZihintntl", "true",
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"'zihintntl' (Non-Temporal Locality Hints)">;
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def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
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AssemblerPredicate<(all_of FeatureStdExtZihintntl),
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"'Zihintntl' (Non-Temporal Locality Hints)">;
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def FeatureStdExtZicsr
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: SubtargetFeature<"zicsr", "HasStdExtZicsr", "true",
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"'zicsr' (CSRs)">;
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def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
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AssemblerPredicate<(all_of FeatureStdExtZicsr),
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"'Zicsr' (CSRs)">;
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def FeatureStdExtZifencei
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: SubtargetFeature<"zifencei", "HasStdExtZifencei", "true",
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"'zifencei' (fence.i)">;
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def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
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AssemblerPredicate<(all_of FeatureStdExtZifencei),
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"'Zifencei' (fence.i)">;
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def FeatureStdExtZfhmin
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: SubtargetFeature<"zfhmin", "HasStdExtZfhmin", "true",
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"'Zfhmin' (Half-Precision Floating-Point Minimal)",
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[FeatureStdExtF]>;
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def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
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AssemblerPredicate<(all_of FeatureStdExtZfhmin),
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"'Zfhmin' (Half-Precision Floating-Point Minimal)">;
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def FeatureStdExtZfh
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: SubtargetFeature<"zfh", "HasStdExtZfh", "true",
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"'Zfh' (Half-Precision Floating-Point)",
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[FeatureStdExtF]>;
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def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
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AssemblerPredicate<(all_of FeatureStdExtZfh),
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"'Zfh' (Half-Precision Floating-Point)">;
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def NoStdExtZfh : Predicate<"!Subtarget->hasStdExtZfh()">;
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def HasStdExtZfhOrZfhmin
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: Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZfhmin()">,
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AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZfhmin),
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"'Zfh' (Half-Precision Floating-Point) or "
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"'Zfhmin' (Half-Precision Floating-Point Minimal)">;
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def FeatureStdExtZfinx
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: SubtargetFeature<"zfinx", "HasStdExtZfinx", "true",
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"'Zfinx' (Float in Integer)">;
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def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
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AssemblerPredicate<(all_of FeatureStdExtZfinx),
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"'Zfinx' (Float in Integer)">;
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def FeatureStdExtZdinx
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: SubtargetFeature<"zdinx", "HasStdExtZdinx", "true",
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"'Zdinx' (Double in Integer)",
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[FeatureStdExtZfinx]>;
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def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
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AssemblerPredicate<(all_of FeatureStdExtZdinx),
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"'Zdinx' (Double in Integer)">;
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def FeatureStdExtZhinxmin
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: SubtargetFeature<"zhinxmin", "HasStdExtZhinxmin", "true",
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"'Zhinxmin' (Half Float in Integer Minimal)",
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[FeatureStdExtZfinx]>;
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def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
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AssemblerPredicate<(all_of FeatureStdExtZhinxmin),
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"'Zhinxmin' (Half Float in Integer Minimal)">;
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def FeatureStdExtZhinx
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: SubtargetFeature<"zhinx", "HasStdExtZhinx", "true",
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"'Zhinx' (Half Float in Integer)",
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[FeatureStdExtZfinx]>;
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def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
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AssemblerPredicate<(all_of FeatureStdExtZhinx),
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"'Zhinx' (Half Float in Integer)">;
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def HasStdExtZhinxOrZhinxmin
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: Predicate<"Subtarget->hasStdExtZhinx() || Subtarget->hasStdExtZhinxmin()">,
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AssemblerPredicate<(any_of FeatureStdExtZhinx, FeatureStdExtZhinxmin),
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"'Zhinx' (Half Float in Integer) or "
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"'Zhinxmin' (Half Float in Integer Minimal)">;
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def FeatureStdExtZfa
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: SubtargetFeature<"experimental-zfa", "HasStdExtZfa", "true",
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"'Zfa' (Additional Floating-Point)",
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[FeatureStdExtF]>;
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def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
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AssemblerPredicate<(all_of FeatureStdExtZfa),
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"'Zfa' (Additional Floating-Point)">;
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def FeatureStdExtC
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: SubtargetFeature<"c", "HasStdExtC", "true",
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"'C' (Compressed Instructions)">;
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def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
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AssemblerPredicate<(all_of FeatureStdExtC),
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"'C' (Compressed Instructions)">;
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def FeatureStdExtZba
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: SubtargetFeature<"zba", "HasStdExtZba", "true",
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"'Zba' (Address Generation Instructions)">;
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def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
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AssemblerPredicate<(all_of FeatureStdExtZba),
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"'Zba' (Address Generation Instructions)">;
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def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
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def FeatureStdExtZbb
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: SubtargetFeature<"zbb", "HasStdExtZbb", "true",
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"'Zbb' (Basic Bit-Manipulation)">;
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def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
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AssemblerPredicate<(all_of FeatureStdExtZbb),
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"'Zbb' (Basic Bit-Manipulation)">;
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def FeatureStdExtZbc
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: SubtargetFeature<"zbc", "HasStdExtZbc", "true",
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"'Zbc' (Carry-Less Multiplication)">;
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def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
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AssemblerPredicate<(all_of FeatureStdExtZbc),
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"'Zbc' (Carry-Less Multiplication)">;
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def FeatureStdExtZbs
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: SubtargetFeature<"zbs", "HasStdExtZbs", "true",
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"'Zbs' (Single-Bit Instructions)">;
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def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
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AssemblerPredicate<(all_of FeatureStdExtZbs),
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"'Zbs' (Single-Bit Instructions)">;
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def FeatureStdExtZbkb
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: SubtargetFeature<"zbkb", "HasStdExtZbkb", "true",
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"'Zbkb' (Bitmanip instructions for Cryptography)">;
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def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
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AssemblerPredicate<(all_of FeatureStdExtZbkb),
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"'Zbkb' (Bitmanip instructions for Cryptography)">;
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def FeatureStdExtZbkx
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: SubtargetFeature<"zbkx", "HasStdExtZbkx", "true",
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"'Zbkx' (Crossbar permutation instructions)">;
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def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">,
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AssemblerPredicate<(all_of FeatureStdExtZbkx),
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"'Zbkx' (Crossbar permutation instructions)">;
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def HasStdExtZbbOrZbkb
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: Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb()">,
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AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbkb),
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"'Zbb' (Basic Bit-Manipulation) or "
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"'Zbkb' (Bitmanip instructions for Cryptography)">;
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// The Carry-less multiply subextension for cryptography is a subset of basic
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// carry-less multiply subextension. The former should be enabled if the latter
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// is enabled.
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def FeatureStdExtZbkc
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: SubtargetFeature<"zbkc", "HasStdExtZbkc", "true",
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"'Zbkc' (Carry-less multiply instructions for "
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"Cryptography)">;
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def HasStdExtZbkc
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: Predicate<"Subtarget->hasStdExtZbkc()">,
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AssemblerPredicate<(all_of FeatureStdExtZbkc),
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"'Zbkc' (Carry-less multiply instructions for Cryptography)">;
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def HasStdExtZbcOrZbkc
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: Predicate<"Subtarget->hasStdExtZbc() || Subtarget->hasStdExtZbkc()">,
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AssemblerPredicate<(any_of FeatureStdExtZbc, FeatureStdExtZbkc),
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"'Zbc' (Carry-Less Multiplication) or "
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"'Zbkc' (Carry-less multiply instructions "
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"for Cryptography)">;
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def FeatureStdExtZknd
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: SubtargetFeature<"zknd", "HasStdExtZknd", "true",
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"'Zknd' (NIST Suite: AES Decryption)">;
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def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">,
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AssemblerPredicate<(all_of FeatureStdExtZknd),
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"'Zknd' (NIST Suite: AES Decryption)">;
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def FeatureStdExtZkne
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: SubtargetFeature<"zkne", "HasStdExtZkne", "true",
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"'Zkne' (NIST Suite: AES Encryption)">;
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def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">,
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AssemblerPredicate<(all_of FeatureStdExtZkne),
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"'Zkne' (NIST Suite: AES Encryption)">;
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// Some instructions belong to both Zknd and Zkne subextensions.
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// They should be enabled if either has been specified.
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def HasStdExtZkndOrZkne
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: Predicate<"Subtarget->hasStdExtZknd() || Subtarget->hasStdExtZkne()">,
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AssemblerPredicate<(any_of FeatureStdExtZknd, FeatureStdExtZkne),
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"'Zknd' (NIST Suite: AES Decryption) or "
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"'Zkne' (NIST Suite: AES Encryption)">;
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def FeatureStdExtZknh
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: SubtargetFeature<"zknh", "HasStdExtZknh", "true",
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"'Zknh' (NIST Suite: Hash Function Instructions)">;
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def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">,
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AssemblerPredicate<(all_of FeatureStdExtZknh),
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"'Zknh' (NIST Suite: Hash Function Instructions)">;
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def FeatureStdExtZksed
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: SubtargetFeature<"zksed", "HasStdExtZksed", "true",
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"'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
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def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">,
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AssemblerPredicate<(all_of FeatureStdExtZksed),
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"'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
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def FeatureStdExtZksh
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: SubtargetFeature<"zksh", "HasStdExtZksh", "true",
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"'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
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def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">,
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AssemblerPredicate<(all_of FeatureStdExtZksh),
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"'Zksh' (ShangMi Suite: SM3 Hash Function "
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"Instructions)">;
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def FeatureStdExtZkr
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: SubtargetFeature<"zkr", "HasStdExtZkr", "true",
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"'Zkr' (Entropy Source Extension)">;
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def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">,
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AssemblerPredicate<(all_of FeatureStdExtZkr),
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"'Zkr' (Entropy Source Extension)">;
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def FeatureStdExtZkn
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: SubtargetFeature<"zkn", "HasStdExtZkn", "true",
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"'Zkn' (NIST Algorithm Suite)",
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[FeatureStdExtZbkb,
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FeatureStdExtZbkc,
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FeatureStdExtZbkx,
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FeatureStdExtZkne,
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FeatureStdExtZknd,
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FeatureStdExtZknh]>;
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def FeatureStdExtZks
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: SubtargetFeature<"zks", "HasStdExtZks", "true",
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"'Zks' (ShangMi Algorithm Suite)",
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[FeatureStdExtZbkb,
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FeatureStdExtZbkc,
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FeatureStdExtZbkx,
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FeatureStdExtZksed,
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FeatureStdExtZksh]>;
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def FeatureStdExtZkt
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: SubtargetFeature<"zkt", "HasStdExtZkt", "true",
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"'Zkt' (Data Independent Execution Latency)">;
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def FeatureStdExtZk
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: SubtargetFeature<"zk", "HasStdExtZk", "true",
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"'Zk' (Standard scalar cryptography extension)",
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[FeatureStdExtZkn,
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FeatureStdExtZkr,
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FeatureStdExtZkt]>;
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def FeatureExtZca
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: SubtargetFeature<"experimental-zca", "HasStdExtZca", "true",
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"'Zca' (part of the C extension, excluding compressed "
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"floating point loads/stores)">;
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def HasStdExtCOrZca
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: Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZca()">,
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AssemblerPredicate<(any_of FeatureStdExtC, FeatureExtZca),
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"'C' (Compressed Instructions) or "
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"'Zca' (part of the C extension, excluding "
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"compressed floating point loads/stores)">;
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def FeatureExtZcb
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: SubtargetFeature<"experimental-zcb", "HasStdExtZcb", "true",
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"'Zcb' (Compressed basic bit manipulation instructions)",
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[FeatureExtZca]>;
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def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
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AssemblerPredicate<(all_of FeatureExtZcb),
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"'Zcb' (Compressed basic bit manipulation instructions)">;
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def FeatureExtZcd
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: SubtargetFeature<"experimental-zcd", "HasStdExtZcd", "true",
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"'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
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def HasStdExtCOrZcd
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: Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcd()">,
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AssemblerPredicate<(any_of FeatureStdExtC, FeatureExtZcd),
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"'C' (Compressed Instructions) or "
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"'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
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def FeatureExtZcf
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: SubtargetFeature<"experimental-zcf", "HasStdExtZcf", "true",
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"'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
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def HasStdExtCOrZcf
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: Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf()">,
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AssemblerPredicate<(any_of FeatureStdExtC, FeatureExtZcf),
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"'C' (Compressed Instructions) or "
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"'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
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def FeatureNoRVCHints
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: SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
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"Disable RVC Hint Instructions.">;
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def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
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AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
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"RVC Hint Instructions">;
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def FeatureStdExtZvl32b : SubtargetFeature<"zvl32b", "ZvlLen", "32",
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"'Zvl' (Minimum Vector Length) 32">;
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foreach i = { 6-16 } in {
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defvar I = !shl(1, i);
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def FeatureStdExtZvl#I#b :
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SubtargetFeature<"zvl"#I#"b", "ZvlLen", !cast<string>(I),
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"'Zvl' (Minimum Vector Length) "#I,
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[!cast<SubtargetFeature>("FeatureStdExtZvl"#!srl(I, 1)#"b")]>;
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}
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def FeatureStdExtZve32x
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: SubtargetFeature<"zve32x", "HasStdExtZve32x", "true",
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"'Zve32x' (Vector Extensions for Embedded Processors "
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"with maximal 32 EEW)",
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[FeatureStdExtZvl32b]>;
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def FeatureStdExtZve32f
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: SubtargetFeature<"zve32f", "HasStdExtZve32f", "true",
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"'Zve32f' (Vector Extensions for Embedded Processors "
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"with maximal 32 EEW and F extension)",
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[FeatureStdExtZve32x]>;
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def FeatureStdExtZve64x
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: SubtargetFeature<"zve64x", "HasStdExtZve64x", "true",
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"'Zve64x' (Vector Extensions for Embedded Processors "
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"with maximal 64 EEW)",
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[FeatureStdExtZve32x, FeatureStdExtZvl64b]>;
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def FeatureStdExtZve64f
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: SubtargetFeature<"zve64f", "HasStdExtZve64f", "true",
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"'Zve64f' (Vector Extensions for Embedded Processors "
|
|
"with maximal 64 EEW and F extension)",
|
|
[FeatureStdExtZve32f, FeatureStdExtZve64x]>;
|
|
|
|
def FeatureStdExtZve64d
|
|
: SubtargetFeature<"zve64d", "HasStdExtZve64d", "true",
|
|
"'Zve64d' (Vector Extensions for Embedded Processors "
|
|
"with maximal 64 EEW, F and D extension)",
|
|
[FeatureStdExtZve64f]>;
|
|
|
|
def FeatureStdExtV
|
|
: SubtargetFeature<"v", "HasStdExtV", "true",
|
|
"'V' (Vector Extension for Application Processors)",
|
|
[FeatureStdExtZvl128b, FeatureStdExtZve64d,
|
|
FeatureStdExtF, FeatureStdExtD]>;
|
|
|
|
def HasVInstructions : Predicate<"Subtarget->hasVInstructions()">,
|
|
AssemblerPredicate<
|
|
(any_of FeatureStdExtZve32x),
|
|
"'V' (Vector Extension for Application Processors), 'Zve32x' or "
|
|
"'Zve64x' (Vector Extensions for Embedded Processors)">;
|
|
def HasVInstructionsI64 : Predicate<"Subtarget->hasVInstructionsI64()">,
|
|
AssemblerPredicate<
|
|
(any_of FeatureStdExtZve64x),
|
|
"'V' (Vector Extension for Application Processors) or 'Zve64x' "
|
|
"(Vector Extensions for Embedded Processors)">;
|
|
def HasVInstructionsAnyF : Predicate<"Subtarget->hasVInstructionsAnyF()">,
|
|
AssemblerPredicate<
|
|
(any_of FeatureStdExtZve32f),
|
|
"'V' (Vector Extension for Application Processors), 'Zve32f', "
|
|
"'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors)">;
|
|
|
|
def FeatureStdExtZvfh
|
|
: SubtargetFeature<"experimental-zvfh", "HasStdExtZvfh", "true",
|
|
"'Zvfh' (Vector Half-Precision Floating-Point)",
|
|
[FeatureStdExtZve32f]>;
|
|
|
|
def FeatureStdExtZicbom
|
|
: SubtargetFeature<"zicbom", "HasStdExtZicbom", "true",
|
|
"'Zicbom' (Cache-Block Management Instructions)">;
|
|
def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
|
|
AssemblerPredicate<(all_of FeatureStdExtZicbom),
|
|
"'Zicbom' (Cache-Block Management Instructions)">;
|
|
|
|
def FeatureStdExtZicboz
|
|
: SubtargetFeature<"zicboz", "HasStdExtZicboz", "true",
|
|
"'Zicboz' (Cache-Block Zero Instructions)">;
|
|
def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
|
|
AssemblerPredicate<(all_of FeatureStdExtZicboz),
|
|
"'Zicboz' (Cache-Block Zero Instructions)">;
|
|
|
|
def FeatureStdExtZicbop
|
|
: SubtargetFeature<"zicbop", "HasStdExtZicbop", "true",
|
|
"'Zicbop' (Cache-Block Prefetch Instructions)">;
|
|
def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
|
|
AssemblerPredicate<(all_of FeatureStdExtZicbop),
|
|
"'Zicbop' (Cache-Block Prefetch Instructions)">;
|
|
|
|
def FeatureStdExtSvnapot
|
|
: SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true",
|
|
"'Svnapot' (NAPOT Translation Contiguity)">;
|
|
|
|
def FeatureStdExtSvpbmt
|
|
: SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true",
|
|
"'Svpbmt' (Page-Based Memory Types)">;
|
|
|
|
def FeatureStdExtSvinval
|
|
: SubtargetFeature<"svinval", "HasStdExtSvinval", "true",
|
|
"'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
|
|
def HasStdExtSvinval : Predicate<"Subtarget->hasStdExtSvinval()">,
|
|
AssemblerPredicate<(all_of FeatureStdExtSvinval),
|
|
"'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
|
|
|
|
def FeatureStdExtZtso
|
|
: SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true",
|
|
"'Ztso' (Memory Model - Total Store Order)">;
|
|
def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZTso()">,
|
|
AssemblerPredicate<(all_of FeatureStdExtZtso),
|
|
"'Ztso' (Memory Model - Total Store Order)">;
|
|
|
|
def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
|
|
"'Zawrs' (Wait on Reservation Set)">;
|
|
def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
|
|
AssemblerPredicate<(all_of FeatureStdExtZawrs),
|
|
"'Zawrs' (Wait on Reservation Set)">;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Vendor extensions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def FeatureVendorXVentanaCondOps
|
|
: SubtargetFeature<"xventanacondops", "HasVendorXVentanaCondOps", "true",
|
|
"'XVentanaCondOps' (Ventana Conditional Ops)">;
|
|
def HasVendorXVentanaCondOps : Predicate<"Subtarget->hasVendorXVentanaCondOps()">,
|
|
AssemblerPredicate<(all_of FeatureVendorXVentanaCondOps),
|
|
"'XVentanaCondOps' (Ventana Conditional Ops)">;
|
|
|
|
def FeatureVendorXTHeadBa
|
|
: SubtargetFeature<"xtheadba", "HasVendorXTHeadBa", "true",
|
|
"'xtheadba' (T-Head address calculation instructions)">;
|
|
def HasVendorXTHeadBa : Predicate<"Subtarget->hasVendorXTHeadBa()">,
|
|
AssemblerPredicate<(all_of FeatureVendorXTHeadBa),
|
|
"'xtheadba' (T-Head address calculation instructions)">;
|
|
|
|
def FeatureVendorXTHeadBb
|
|
: SubtargetFeature<"xtheadbb", "HasVendorXTHeadBb", "true",
|
|
"'xtheadbb' (T-Head basic bit-manipulation instructions)">;
|
|
def HasVendorXTHeadBb : Predicate<"Subtarget->hasVendorXTHeadBb()">,
|
|
AssemblerPredicate<(all_of FeatureVendorXTHeadBb),
|
|
"'xtheadbb' (T-Head basic bit-manipulation instructions)">;
|
|
|
|
def FeatureVendorXTHeadBs
|
|
: SubtargetFeature<"xtheadbs", "HasVendorXTHeadBs", "true",
|
|
"'xtheadbs' (T-Head single-bit instructions)">;
|
|
def HasVendorXTHeadBs : Predicate<"Subtarget->hasVendorXTHeadBs()">,
|
|
AssemblerPredicate<(all_of FeatureVendorXTHeadBs),
|
|
"'xtheadbs' (T-Head single-bit instructions)">;
|
|
|
|
def FeatureVendorXTHeadMac
|
|
: SubtargetFeature<"xtheadmac", "HasVendorXTHeadMac", "true",
|
|
"'xtheadmac' (T-Head Multiply-Accumulate Instructions)">;
|
|
def HasVendorXTHeadMac : Predicate<"Subtarget->hasVendorXTHeadMac()">,
|
|
AssemblerPredicate<(all_of FeatureVendorXTHeadMac),
|
|
"'xtheadmac' (T-Head Multiply-Accumulate Instructions)">;
|
|
|
|
def FeatureVendorXTHeadVdot
|
|
: SubtargetFeature<"xtheadvdot", "HasVendorXTHeadVdot", "true",
|
|
"'xtheadvdot' (T-Head Vector Extensions for Dot)",
|
|
[FeatureStdExtV]>;
|
|
def HasVendorXTHeadVdot : Predicate<"Subtarget->hasVendorXTHeadVdot()">,
|
|
AssemblerPredicate<(all_of FeatureVendorXTHeadVdot),
|
|
"'xtheadvdot' (T-Head Vector Extensions for Dot)">;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// LLVM specific features and extensions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
|
|
// tuning CPU names.
|
|
def Feature32Bit
|
|
: SubtargetFeature<"32bit", "HasRV32", "true", "Implements RV32">;
|
|
def Feature64Bit
|
|
: SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
|
|
def IsRV64 : Predicate<"Subtarget->is64Bit()">,
|
|
AssemblerPredicate<(all_of Feature64Bit),
|
|
"RV64I Base Instruction Set">;
|
|
def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
|
|
AssemblerPredicate<(all_of (not Feature64Bit)),
|
|
"RV32I Base Instruction Set">;
|
|
|
|
defvar RV32 = DefaultMode;
|
|
def RV64 : HwMode<"+64bit">;
|
|
|
|
def FeatureRV32E
|
|
: SubtargetFeature<"e", "IsRV32E", "true",
|
|
"Implements RV32E (provides 16 rather than 32 GPRs)">;
|
|
def IsRV32E : Predicate<"Subtarget->isRV32E()">,
|
|
AssemblerPredicate<(all_of FeatureRV32E)>;
|
|
|
|
def FeatureRelax
|
|
: SubtargetFeature<"relax", "EnableLinkerRelax", "true",
|
|
"Enable Linker relaxation.">;
|
|
|
|
foreach i = {1-31} in
|
|
def FeatureReserveX#i :
|
|
SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]",
|
|
"true", "Reserve X"#i>;
|
|
|
|
def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore",
|
|
"true", "Enable save/restore.">;
|
|
|
|
def FeatureUnalignedScalarMem
|
|
: SubtargetFeature<"unaligned-scalar-mem", "EnableUnalignedScalarMem",
|
|
"true", "Has reasonably performant unaligned scalar "
|
|
"loads and stores">;
|
|
|
|
def TuneNoOptimizedZeroStrideLoad
|
|
: SubtargetFeature<"no-optimized-zero-stride-load", "HasOptimizedZeroStrideLoad",
|
|
"false", "Hasn't optimized (perform fewer memory operations)"
|
|
"zero-stride vector load">;
|
|
|
|
def TuneLUIADDIFusion
|
|
: SubtargetFeature<"lui-addi-fusion", "HasLUIADDIFusion",
|
|
"true", "Enable LUI+ADDI macrofusion">;
|
|
|
|
def TuneNoDefaultUnroll
|
|
: SubtargetFeature<"no-default-unroll", "EnableDefaultUnroll", "false",
|
|
"Disable default unroll preference.">;
|
|
|
|
// SiFive 7 is able to fuse integer ALU operations with a preceding branch
|
|
// instruction.
|
|
def TuneShortForwardBranchOpt
|
|
: SubtargetFeature<"short-forward-branch-opt", "HasShortForwardBranchOpt",
|
|
"true", "Enable short forward branch optimization">;
|
|
def HasShortForwardBranchOpt : Predicate<"Subtarget->hasShortForwardBranchOpt()">;
|
|
def NoShortForwardBranchOpt : Predicate<"!Subtarget->hasShortForwardBranchOpt()">;
|
|
|
|
def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
|
|
"SiFive 7-Series processors",
|
|
[TuneNoDefaultUnroll,
|
|
TuneShortForwardBranchOpt]>;
|
|
|
|
// Assume that lock-free native-width atomics are available, even if the target
|
|
// and operating system combination would not usually provide them. The user
|
|
// is responsible for providing any necessary __sync implementations. Code
|
|
// built with this feature is not ABI-compatible with code built without this
|
|
// feature, if atomic variables are exposed across the ABI boundary.
|
|
def FeatureForcedAtomics : SubtargetFeature<
|
|
"forced-atomics", "HasForcedAtomics", "true",
|
|
"Assume that lock-free native-width atomics are available">;
|
|
def HasAtomicLdSt
|
|
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasForcedAtomics()">;
|
|
|
|
def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
|
|
"AllowTaggedGlobals",
|
|
"true", "Use an instruction sequence for taking the address of a global "
|
|
"that allows a memory tag in the upper address bits">;
|