500 lines
17 KiB
LLVM
500 lines
17 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S %s -passes=loop-instsimplify | FileCheck %s
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; RUN: opt -S %s -passes='loop-mssa(loop-instsimplify)' -verify-memoryssa | FileCheck %s
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; TODO: turn to %iv <u umin(inv_1, inv_2) and hoist it out of loop.
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define i32 @test_ult(i32 %start, i32 %inv_1, i32 %inv_2) {
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; CHECK-LABEL: @test_ult(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[CMP_1:%.*]] = icmp ult i32 [[IV]], [[INV_1:%.*]]
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; CHECK-NEXT: [[CMP_2:%.*]] = icmp ult i32 [[IV]], [[INV_2:%.*]]
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; CHECK-NEXT: [[LOOP_COND:%.*]] = and i1 [[CMP_1]], [[CMP_2]]
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[LOOP]] ]
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; CHECK-NEXT: ret i32 [[IV_LCSSA]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [%start, %entry], [%iv.next, %loop]
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%cmp_1 = icmp ult i32 %iv, %inv_1
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%cmp_2 = icmp ult i32 %iv, %inv_2
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%loop_cond = and i1 %cmp_1, %cmp_2
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%iv.next = add i32 %iv, 1
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br i1 %loop_cond, label %loop, label %exit
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exit:
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ret i32 %iv
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}
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; TODO: turn to %iv <=u umin(inv_1, inv_2) and hoist it out of loop.
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define i32 @test_ule(i32 %start, i32 %inv_1, i32 %inv_2) {
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; CHECK-LABEL: @test_ule(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[CMP_1:%.*]] = icmp ule i32 [[IV]], [[INV_1:%.*]]
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; CHECK-NEXT: [[CMP_2:%.*]] = icmp ule i32 [[IV]], [[INV_2:%.*]]
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; CHECK-NEXT: [[LOOP_COND:%.*]] = and i1 [[CMP_1]], [[CMP_2]]
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[LOOP]] ]
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; CHECK-NEXT: ret i32 [[IV_LCSSA]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [%start, %entry], [%iv.next, %loop]
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%cmp_1 = icmp ule i32 %iv, %inv_1
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%cmp_2 = icmp ule i32 %iv, %inv_2
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%loop_cond = and i1 %cmp_1, %cmp_2
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%iv.next = add i32 %iv, 1
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br i1 %loop_cond, label %loop, label %exit
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exit:
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ret i32 %iv
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}
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; TODO: turn to %iv <s smin(inv_1, inv_2) and hoist it out of loop.
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define i32 @test_slt(i32 %start, i32 %inv_1, i32 %inv_2) {
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; CHECK-LABEL: @test_slt(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[CMP_1:%.*]] = icmp slt i32 [[IV]], [[INV_1:%.*]]
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; CHECK-NEXT: [[CMP_2:%.*]] = icmp slt i32 [[IV]], [[INV_2:%.*]]
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; CHECK-NEXT: [[LOOP_COND:%.*]] = and i1 [[CMP_1]], [[CMP_2]]
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[LOOP]] ]
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; CHECK-NEXT: ret i32 [[IV_LCSSA]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [%start, %entry], [%iv.next, %loop]
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%cmp_1 = icmp slt i32 %iv, %inv_1
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%cmp_2 = icmp slt i32 %iv, %inv_2
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%loop_cond = and i1 %cmp_1, %cmp_2
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%iv.next = add i32 %iv, 1
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br i1 %loop_cond, label %loop, label %exit
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exit:
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ret i32 %iv
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}
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; TODO: turn to %iv <=s smin(inv_1, inv_2) and hoist it out of loop.
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define i32 @test_sle(i32 %start, i32 %inv_1, i32 %inv_2) {
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; CHECK-LABEL: @test_sle(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[CMP_1:%.*]] = icmp sle i32 [[IV]], [[INV_1:%.*]]
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; CHECK-NEXT: [[CMP_2:%.*]] = icmp sle i32 [[IV]], [[INV_2:%.*]]
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; CHECK-NEXT: [[LOOP_COND:%.*]] = and i1 [[CMP_1]], [[CMP_2]]
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[LOOP]] ]
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; CHECK-NEXT: ret i32 [[IV_LCSSA]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [%start, %entry], [%iv.next, %loop]
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%cmp_1 = icmp sle i32 %iv, %inv_1
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%cmp_2 = icmp sle i32 %iv, %inv_2
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%loop_cond = and i1 %cmp_1, %cmp_2
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%iv.next = add i32 %iv, 1
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br i1 %loop_cond, label %loop, label %exit
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exit:
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ret i32 %iv
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}
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; TODO: turn to %iv >u umax(inv_1, inv_2) and hoist it out of loop.
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define i32 @test_ugt(i32 %start, i32 %inv_1, i32 %inv_2) {
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; CHECK-LABEL: @test_ugt(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[CMP_1:%.*]] = icmp ugt i32 [[IV]], [[INV_1:%.*]]
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; CHECK-NEXT: [[CMP_2:%.*]] = icmp ugt i32 [[IV]], [[INV_2:%.*]]
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; CHECK-NEXT: [[LOOP_COND:%.*]] = and i1 [[CMP_1]], [[CMP_2]]
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[LOOP]] ]
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; CHECK-NEXT: ret i32 [[IV_LCSSA]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [%start, %entry], [%iv.next, %loop]
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%cmp_1 = icmp ugt i32 %iv, %inv_1
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%cmp_2 = icmp ugt i32 %iv, %inv_2
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%loop_cond = and i1 %cmp_1, %cmp_2
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%iv.next = add i32 %iv, 1
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br i1 %loop_cond, label %loop, label %exit
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exit:
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ret i32 %iv
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}
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; TODO: turn to %iv >=u umax(inv_1, inv_2) and hoist it out of loop.
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define i32 @test_uge(i32 %start, i32 %inv_1, i32 %inv_2) {
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; CHECK-LABEL: @test_uge(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[CMP_1:%.*]] = icmp uge i32 [[IV]], [[INV_1:%.*]]
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; CHECK-NEXT: [[CMP_2:%.*]] = icmp uge i32 [[IV]], [[INV_2:%.*]]
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; CHECK-NEXT: [[LOOP_COND:%.*]] = and i1 [[CMP_1]], [[CMP_2]]
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[LOOP]] ]
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; CHECK-NEXT: ret i32 [[IV_LCSSA]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [%start, %entry], [%iv.next, %loop]
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%cmp_1 = icmp uge i32 %iv, %inv_1
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%cmp_2 = icmp uge i32 %iv, %inv_2
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%loop_cond = and i1 %cmp_1, %cmp_2
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%iv.next = add i32 %iv, 1
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br i1 %loop_cond, label %loop, label %exit
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exit:
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ret i32 %iv
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}
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; TODO: turn to %iv >s smax(inv_1, inv_2) and hoist it out of loop.
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define i32 @test_sgt(i32 %start, i32 %inv_1, i32 %inv_2) {
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; CHECK-LABEL: @test_sgt(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[CMP_1:%.*]] = icmp sgt i32 [[IV]], [[INV_1:%.*]]
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; CHECK-NEXT: [[CMP_2:%.*]] = icmp sgt i32 [[IV]], [[INV_2:%.*]]
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; CHECK-NEXT: [[LOOP_COND:%.*]] = and i1 [[CMP_1]], [[CMP_2]]
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[LOOP]] ]
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; CHECK-NEXT: ret i32 [[IV_LCSSA]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [%start, %entry], [%iv.next, %loop]
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%cmp_1 = icmp sgt i32 %iv, %inv_1
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%cmp_2 = icmp sgt i32 %iv, %inv_2
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%loop_cond = and i1 %cmp_1, %cmp_2
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%iv.next = add i32 %iv, 1
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br i1 %loop_cond, label %loop, label %exit
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exit:
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ret i32 %iv
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}
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; TODO: turn to %iv >=s smax(inv_1, inv_2) and hoist it out of loop.
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define i32 @test_sge(i32 %start, i32 %inv_1, i32 %inv_2) {
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; CHECK-LABEL: @test_sge(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[CMP_1:%.*]] = icmp sge i32 [[IV]], [[INV_1:%.*]]
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; CHECK-NEXT: [[CMP_2:%.*]] = icmp sge i32 [[IV]], [[INV_2:%.*]]
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; CHECK-NEXT: [[LOOP_COND:%.*]] = and i1 [[CMP_1]], [[CMP_2]]
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[LOOP]] ]
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; CHECK-NEXT: ret i32 [[IV_LCSSA]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [%start, %entry], [%iv.next, %loop]
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%cmp_1 = icmp sge i32 %iv, %inv_1
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%cmp_2 = icmp sge i32 %iv, %inv_2
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%loop_cond = and i1 %cmp_1, %cmp_2
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%iv.next = add i32 %iv, 1
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br i1 %loop_cond, label %loop, label %exit
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exit:
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ret i32 %iv
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}
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; TODO: Turn OR to AND and handle accordingly.
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define i32 @test_ult_inv(i32 %start, i32 %inv_1, i32 %inv_2) {
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; CHECK-LABEL: @test_ult_inv(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[CMP_1:%.*]] = icmp ult i32 [[IV]], [[INV_1:%.*]]
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; CHECK-NEXT: [[CMP_2:%.*]] = icmp ult i32 [[IV]], [[INV_2:%.*]]
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; CHECK-NEXT: [[LOOP_COND:%.*]] = or i1 [[CMP_1]], [[CMP_2]]
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[LOOP]] ]
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; CHECK-NEXT: ret i32 [[IV_LCSSA]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [%start, %entry], [%iv.next, %loop]
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%cmp_1 = icmp ult i32 %iv, %inv_1
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%cmp_2 = icmp ult i32 %iv, %inv_2
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%loop_cond = or i1 %cmp_1, %cmp_2
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%iv.next = add i32 %iv, 1
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br i1 %loop_cond, label %loop, label %exit
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exit:
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ret i32 %iv
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}
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; TODO: Turn OR to AND and handle accordingly.
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define i32 @test_ule_inv(i32 %start, i32 %inv_1, i32 %inv_2) {
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; CHECK-LABEL: @test_ule_inv(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[CMP_1:%.*]] = icmp ule i32 [[IV]], [[INV_1:%.*]]
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; CHECK-NEXT: [[CMP_2:%.*]] = icmp ule i32 [[IV]], [[INV_2:%.*]]
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; CHECK-NEXT: [[LOOP_COND:%.*]] = or i1 [[CMP_1]], [[CMP_2]]
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[LOOP]] ]
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; CHECK-NEXT: ret i32 [[IV_LCSSA]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [%start, %entry], [%iv.next, %loop]
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%cmp_1 = icmp ule i32 %iv, %inv_1
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%cmp_2 = icmp ule i32 %iv, %inv_2
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%loop_cond = or i1 %cmp_1, %cmp_2
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%iv.next = add i32 %iv, 1
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br i1 %loop_cond, label %loop, label %exit
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exit:
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ret i32 %iv
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}
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; TODO: Turn OR to AND and handle accordingly.
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define i32 @test_slt_inv(i32 %start, i32 %inv_1, i32 %inv_2) {
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; CHECK-LABEL: @test_slt_inv(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[CMP_1:%.*]] = icmp slt i32 [[IV]], [[INV_1:%.*]]
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; CHECK-NEXT: [[CMP_2:%.*]] = icmp slt i32 [[IV]], [[INV_2:%.*]]
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; CHECK-NEXT: [[LOOP_COND:%.*]] = or i1 [[CMP_1]], [[CMP_2]]
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[LOOP]] ]
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; CHECK-NEXT: ret i32 [[IV_LCSSA]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [%start, %entry], [%iv.next, %loop]
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%cmp_1 = icmp slt i32 %iv, %inv_1
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%cmp_2 = icmp slt i32 %iv, %inv_2
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%loop_cond = or i1 %cmp_1, %cmp_2
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%iv.next = add i32 %iv, 1
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br i1 %loop_cond, label %loop, label %exit
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exit:
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ret i32 %iv
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}
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; TODO: Turn OR to AND and handle accordingly.
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define i32 @test_sle_inv(i32 %start, i32 %inv_1, i32 %inv_2) {
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; CHECK-LABEL: @test_sle_inv(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[CMP_1:%.*]] = icmp sle i32 [[IV]], [[INV_1:%.*]]
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; CHECK-NEXT: [[CMP_2:%.*]] = icmp sle i32 [[IV]], [[INV_2:%.*]]
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; CHECK-NEXT: [[LOOP_COND:%.*]] = or i1 [[CMP_1]], [[CMP_2]]
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[LOOP]] ]
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; CHECK-NEXT: ret i32 [[IV_LCSSA]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [%start, %entry], [%iv.next, %loop]
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%cmp_1 = icmp sle i32 %iv, %inv_1
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%cmp_2 = icmp sle i32 %iv, %inv_2
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%loop_cond = or i1 %cmp_1, %cmp_2
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%iv.next = add i32 %iv, 1
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br i1 %loop_cond, label %loop, label %exit
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exit:
|
|
ret i32 %iv
|
|
}
|
|
|
|
; TODO: Turn OR to AND and handle accordingly.
|
|
define i32 @test_ugt_inv(i32 %start, i32 %inv_1, i32 %inv_2) {
|
|
; CHECK-LABEL: @test_ugt_inv(
|
|
; CHECK-NEXT: entry:
|
|
; CHECK-NEXT: br label [[LOOP:%.*]]
|
|
; CHECK: loop:
|
|
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
|
|
; CHECK-NEXT: [[CMP_1:%.*]] = icmp ugt i32 [[IV]], [[INV_1:%.*]]
|
|
; CHECK-NEXT: [[CMP_2:%.*]] = icmp ugt i32 [[IV]], [[INV_2:%.*]]
|
|
; CHECK-NEXT: [[LOOP_COND:%.*]] = or i1 [[CMP_1]], [[CMP_2]]
|
|
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
|
|
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
|
|
; CHECK: exit:
|
|
; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[LOOP]] ]
|
|
; CHECK-NEXT: ret i32 [[IV_LCSSA]]
|
|
;
|
|
entry:
|
|
br label %loop
|
|
|
|
loop:
|
|
%iv = phi i32 [%start, %entry], [%iv.next, %loop]
|
|
%cmp_1 = icmp ugt i32 %iv, %inv_1
|
|
%cmp_2 = icmp ugt i32 %iv, %inv_2
|
|
%loop_cond = or i1 %cmp_1, %cmp_2
|
|
%iv.next = add i32 %iv, 1
|
|
br i1 %loop_cond, label %loop, label %exit
|
|
|
|
exit:
|
|
ret i32 %iv
|
|
}
|
|
|
|
; TODO: Turn OR to AND and handle accordingly.
|
|
define i32 @test_uge_inv(i32 %start, i32 %inv_1, i32 %inv_2) {
|
|
; CHECK-LABEL: @test_uge_inv(
|
|
; CHECK-NEXT: entry:
|
|
; CHECK-NEXT: br label [[LOOP:%.*]]
|
|
; CHECK: loop:
|
|
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
|
|
; CHECK-NEXT: [[CMP_1:%.*]] = icmp uge i32 [[IV]], [[INV_1:%.*]]
|
|
; CHECK-NEXT: [[CMP_2:%.*]] = icmp uge i32 [[IV]], [[INV_2:%.*]]
|
|
; CHECK-NEXT: [[LOOP_COND:%.*]] = or i1 [[CMP_1]], [[CMP_2]]
|
|
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
|
|
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
|
|
; CHECK: exit:
|
|
; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[LOOP]] ]
|
|
; CHECK-NEXT: ret i32 [[IV_LCSSA]]
|
|
;
|
|
entry:
|
|
br label %loop
|
|
|
|
loop:
|
|
%iv = phi i32 [%start, %entry], [%iv.next, %loop]
|
|
%cmp_1 = icmp uge i32 %iv, %inv_1
|
|
%cmp_2 = icmp uge i32 %iv, %inv_2
|
|
%loop_cond = or i1 %cmp_1, %cmp_2
|
|
%iv.next = add i32 %iv, 1
|
|
br i1 %loop_cond, label %loop, label %exit
|
|
|
|
exit:
|
|
ret i32 %iv
|
|
}
|
|
|
|
; TODO: Turn OR to AND and handle accordingly.
|
|
define i32 @test_sgt_inv(i32 %start, i32 %inv_1, i32 %inv_2) {
|
|
; CHECK-LABEL: @test_sgt_inv(
|
|
; CHECK-NEXT: entry:
|
|
; CHECK-NEXT: br label [[LOOP:%.*]]
|
|
; CHECK: loop:
|
|
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
|
|
; CHECK-NEXT: [[CMP_1:%.*]] = icmp sgt i32 [[IV]], [[INV_1:%.*]]
|
|
; CHECK-NEXT: [[CMP_2:%.*]] = icmp sgt i32 [[IV]], [[INV_2:%.*]]
|
|
; CHECK-NEXT: [[LOOP_COND:%.*]] = or i1 [[CMP_1]], [[CMP_2]]
|
|
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
|
|
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
|
|
; CHECK: exit:
|
|
; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[LOOP]] ]
|
|
; CHECK-NEXT: ret i32 [[IV_LCSSA]]
|
|
;
|
|
entry:
|
|
br label %loop
|
|
|
|
loop:
|
|
%iv = phi i32 [%start, %entry], [%iv.next, %loop]
|
|
%cmp_1 = icmp sgt i32 %iv, %inv_1
|
|
%cmp_2 = icmp sgt i32 %iv, %inv_2
|
|
%loop_cond = or i1 %cmp_1, %cmp_2
|
|
%iv.next = add i32 %iv, 1
|
|
br i1 %loop_cond, label %loop, label %exit
|
|
|
|
exit:
|
|
ret i32 %iv
|
|
}
|
|
|
|
; TODO: Turn OR to AND and handle accordingly.
|
|
define i32 @test_sge_inv(i32 %start, i32 %inv_1, i32 %inv_2) {
|
|
; CHECK-LABEL: @test_sge_inv(
|
|
; CHECK-NEXT: entry:
|
|
; CHECK-NEXT: br label [[LOOP:%.*]]
|
|
; CHECK: loop:
|
|
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
|
|
; CHECK-NEXT: [[CMP_1:%.*]] = icmp sge i32 [[IV]], [[INV_1:%.*]]
|
|
; CHECK-NEXT: [[CMP_2:%.*]] = icmp sge i32 [[IV]], [[INV_2:%.*]]
|
|
; CHECK-NEXT: [[LOOP_COND:%.*]] = or i1 [[CMP_1]], [[CMP_2]]
|
|
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
|
|
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
|
|
; CHECK: exit:
|
|
; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[LOOP]] ]
|
|
; CHECK-NEXT: ret i32 [[IV_LCSSA]]
|
|
;
|
|
entry:
|
|
br label %loop
|
|
|
|
loop:
|
|
%iv = phi i32 [%start, %entry], [%iv.next, %loop]
|
|
%cmp_1 = icmp sge i32 %iv, %inv_1
|
|
%cmp_2 = icmp sge i32 %iv, %inv_2
|
|
%loop_cond = or i1 %cmp_1, %cmp_2
|
|
%iv.next = add i32 %iv, 1
|
|
br i1 %loop_cond, label %loop, label %exit
|
|
|
|
exit:
|
|
ret i32 %iv
|
|
}
|