f3efbce4a7
Clang and other frontends generally need the LLVM data layout string in
order to generate LLVM IR modules for LLVM. MLIR clients often need it
as well, since MLIR users often lower to LLVM IR.
Before this change, the LLVM datalayout string was computed in the
LLVM${TGT}CodeGen library in the relevant TargetMachine subclass.
However, none of the logic for computing the data layout string requires
any details of code generation. Clients who want to avoid duplicating
this information were forced to link in LLVMCodeGen and all registered
targets, leading to bloated binaries. This happened in PR #145899,
which measurably increased binary size for some of our users.
By moving this information to the TargetParser library, we
can delete the duplicate datalayout strings in Clang, and retain the
ability to generate IR for unregistered targets.
This is intended to be a very mechanical LLVM-only change, but there is
an immediately obvious follow-up to clang, which will be prepared
separately.
The vast majority of data layouts are computable with two inputs: the
triple and the "ABI name". There is only one exception, NVPTX, which has
a cl::opt to enable short device pointers. I invented a "shortptr" ABI
name to pass this option through the target independent interface.
Everything else fits. Mips is a bit awkward because it uses a special
MipsABIInfo abstraction, which includes members with codegen-like
concepts like ABI physical registers that can't live in TargetParser. I
think the string logic of looking for "n32" "n64" etc is reasonable to
duplicate. We have plenty of other minor duplication to preserve
layering.
---------
Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
Co-authored-by: Sergei Barannikov <barannikov88@gmail.com>
130 lines
3.6 KiB
C++
130 lines
3.6 KiB
C++
//===---- MipsABIInfo.cpp - Information about MIPS ABI's ------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "MipsABIInfo.h"
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#include "Mips.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/MC/MCTargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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// Note: this option is defined here to be visible from libLLVMMipsAsmParser
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// and libLLVMMipsCodeGen
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cl::opt<bool>
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EmitJalrReloc("mips-jalr-reloc", cl::Hidden,
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cl::desc("MIPS: Emit R_{MICRO}MIPS_JALR relocation with jalr"),
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cl::init(true));
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namespace {
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static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
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static const MCPhysReg Mips64IntRegs[8] = {
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Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
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Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
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}
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ArrayRef<MCPhysReg> MipsABIInfo::GetByValArgRegs() const {
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if (IsO32())
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return ArrayRef(O32IntRegs);
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if (IsN32() || IsN64())
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return ArrayRef(Mips64IntRegs);
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llvm_unreachable("Unhandled ABI");
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}
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ArrayRef<MCPhysReg> MipsABIInfo::getVarArgRegs(bool isGP64bit) const {
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if (IsO32()) {
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if (isGP64bit)
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return ArrayRef(Mips64IntRegs);
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else
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return ArrayRef(O32IntRegs);
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}
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if (IsN32() || IsN64())
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return ArrayRef(Mips64IntRegs);
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llvm_unreachable("Unhandled ABI");
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}
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unsigned MipsABIInfo::GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const {
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if (IsO32())
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return CC != CallingConv::Fast ? 16 : 0;
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if (IsN32() || IsN64())
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return 0;
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llvm_unreachable("Unhandled ABI");
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}
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MipsABIInfo MipsABIInfo::computeTargetABI(const Triple &TT, StringRef ABIName) {
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if (ABIName.starts_with("o32"))
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return MipsABIInfo::O32();
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if (ABIName.starts_with("n32"))
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return MipsABIInfo::N32();
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if (ABIName.starts_with("n64"))
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return MipsABIInfo::N64();
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if (TT.isABIN32())
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return MipsABIInfo::N32();
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assert(ABIName.empty() && "Unknown ABI option for MIPS");
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if (TT.isMIPS64())
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return MipsABIInfo::N64();
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return MipsABIInfo::O32();
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}
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unsigned MipsABIInfo::GetStackPtr() const {
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return ArePtrs64bit() ? Mips::SP_64 : Mips::SP;
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}
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unsigned MipsABIInfo::GetFramePtr() const {
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return ArePtrs64bit() ? Mips::FP_64 : Mips::FP;
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}
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unsigned MipsABIInfo::GetBasePtr() const {
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return ArePtrs64bit() ? Mips::S7_64 : Mips::S7;
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}
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unsigned MipsABIInfo::GetGlobalPtr() const {
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return ArePtrs64bit() ? Mips::GP_64 : Mips::GP;
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}
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unsigned MipsABIInfo::GetNullPtr() const {
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return ArePtrs64bit() ? Mips::ZERO_64 : Mips::ZERO;
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}
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unsigned MipsABIInfo::GetZeroReg() const {
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return AreGprs64bit() ? Mips::ZERO_64 : Mips::ZERO;
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}
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unsigned MipsABIInfo::GetPtrAdduOp() const {
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return ArePtrs64bit() ? Mips::DADDu : Mips::ADDu;
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}
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unsigned MipsABIInfo::GetPtrAddiuOp() const {
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return ArePtrs64bit() ? Mips::DADDiu : Mips::ADDiu;
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}
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unsigned MipsABIInfo::GetPtrSubuOp() const {
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return ArePtrs64bit() ? Mips::DSUBu : Mips::SUBu;
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}
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unsigned MipsABIInfo::GetPtrAndOp() const {
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return ArePtrs64bit() ? Mips::AND64 : Mips::AND;
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}
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unsigned MipsABIInfo::GetGPRMoveOp() const {
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return ArePtrs64bit() ? Mips::OR64 : Mips::OR;
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}
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unsigned MipsABIInfo::GetEhDataReg(unsigned I) const {
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static const unsigned EhDataReg[] = {
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Mips::A0, Mips::A1, Mips::A2, Mips::A3
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};
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static const unsigned EhDataReg64[] = {
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Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64
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};
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return IsN64() ? EhDataReg64[I] : EhDataReg[I];
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}
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