9630b321a5
This patch aims at making the combination of single-float and N32/N64 ABI properly work. Right now when both options are enabled the compiler chooses an incorrect ABI and in some cases even generates wrong instructions. The floating point behavior on MIPS is controlled through 3 flags: soft-float, single-float, fp64. This makes things complicated because fp64 indicates the presence of 64bit floating point registers, but cannot be easily disabled (the mips3 feature require it, but mips3 CPUs with only 32bit floating point exist). Also if fp64 is missing it doesn't actually disable 64bit floating point operations, because certain MIPS1/2 CPUs support 64bit floating point with 32bit registers, hence the single-float option. I'm guessing that originally single-float was only intended for the latter case, and that's the reason why it doesn't properly work on 64bit targets. So this patch does the following: - Make single-float a "master disable", even if fp64 is enabled this should completely disable generation of 64bit floating point operations, making it available on targets which hard require fp64. - Add proper calling conventions for N32/N64 single-float combinations. - Fixup codegen to not generate certain 64bit floating point operations, apparently not assigning a register class to f64 values is not enough to prevent them from showing up. - Add tests for the new calling conventions and codegen.
404 lines
17 KiB
TableGen
404 lines
17 KiB
TableGen
//===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// This describes the calling conventions for Mips architecture.
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//===----------------------------------------------------------------------===//
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/// CCIfSubtarget - Match if the current subtarget has a feature F.
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class CCIfSubtarget<string F, CCAction A, string Invert = "">
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: CCIf<!strconcat(Invert,
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"State.getMachineFunction().getSubtarget<MipsSubtarget>().",
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F),
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A>;
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// The inverse of CCIfSubtarget
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class CCIfSubtargetNot<string F, CCAction A> : CCIfSubtarget<F, A, "!">;
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/// Match if the original argument (before lowering) was a float.
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/// For example, this is true for i32's that were lowered from soft-float.
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class CCIfOrigArgWasFloat<CCAction A> : CCIf<"OrigTy->isFloatingPointTy()", A>;
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/// Match if the original argument (before lowering) was a 128-bit float (i.e.
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/// long double).
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class CCIfOrigArgWasF128<CCAction A> : CCIf<"OrigTy->isFP128Ty()", A>;
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/// Match if the return was not a floating point vector.
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class CCIfOrigArgWasNotVectorFloat<CCAction A>
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: CCIf<"!OrigTy->isVectorTy() || !OrigTy->isFPOrFPVectorTy()", A>;
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/// Match if the special calling conv is the specified value.
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class CCIfSpecialCallingConv<string CC, CCAction A>
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: CCIf<"static_cast<MipsCCState *>(&State)->getSpecialCallingConv() == "
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"MipsCCState::" # CC, A>;
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// For soft-float, f128 values are returned in A0_64 rather than V1_64.
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def RetCC_F128SoftFloat : CallingConv<[
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CCAssignToReg<[V0_64, A0_64]>
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]>;
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// For hard-float, f128 values are returned as a pair of f64's rather than a
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// pair of i64's.
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def RetCC_F128HardFloat : CallingConv<[
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CCBitConvertToType<f64>,
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// Contrary to the ABI documentation, a struct containing a long double is
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// returned in $f0, and $f1 instead of the usual $f0, and $f2. This is to
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// match the de facto ABI as implemented by GCC.
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CCIfInReg<CCAssignToReg<[D0_64, D1_64]>>,
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CCAssignToReg<[D0_64, D2_64]>
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]>;
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// Handle F128 specially since we can't identify the original type during the
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// tablegen-erated code.
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def RetCC_F128 : CallingConv<[
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CCIfSubtarget<"useSoftFloat()",
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CCIfType<[i64], CCDelegateTo<RetCC_F128SoftFloat>>>,
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CCIfSubtargetNot<"useSoftFloat()",
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CCIfType<[i64], CCDelegateTo<RetCC_F128HardFloat>>>
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]>;
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//===----------------------------------------------------------------------===//
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// Mips O32 Calling Convention
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//===----------------------------------------------------------------------===//
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def CC_MipsO32 : CallingConv<[
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// Promote i8/i16 arguments to i32.
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CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
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// Integer values get stored in stack slots that are 4 bytes in
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// size and 4-byte aligned.
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CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
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// Integer values get stored in stack slots that are 8 bytes in
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// size and 8-byte aligned.
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CCIfType<[f64], CCAssignToStack<8, 8>>
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]>;
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// Only the return rules are defined here for O32. The rules for argument
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// passing are defined in MipsISelLowering.cpp.
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def RetCC_MipsO32 : CallingConv<[
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// Promote i1/i8/i16 return values to i32.
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CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
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// i32 are returned in registers V0, V1, A0, A1, unless the original return
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// type was a vector of floats.
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CCIfOrigArgWasNotVectorFloat<CCIfType<[i32],
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CCAssignToReg<[V0, V1, A0, A1]>>>,
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// f32 are returned in registers F0, F2
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CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
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// f64 arguments are returned in D0_64 and D2_64 in FP64bit mode or
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// in D0 and D1 in FP32bit mode.
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CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D2_64]>>>,
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CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()", CCAssignToReg<[D0, D1]>>>
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]>;
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def CC_MipsO32_FP32 : CustomCallingConv;
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def CC_MipsO32_FP64 : CustomCallingConv;
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def CC_MipsO32_FP : CallingConv<[
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CCIfSubtargetNot<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP32>>,
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CCIfSubtarget<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP64>>
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]>;
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//===----------------------------------------------------------------------===//
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// Mips N32/64 Calling Convention
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//===----------------------------------------------------------------------===//
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def CC_MipsN_SoftFloat : CallingConv<[
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CCAssignToRegWithShadow<[A0, A1, A2, A3,
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T0, T1, T2, T3],
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[D12_64, D13_64, D14_64, D15_64,
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D16_64, D17_64, D18_64, D19_64]>,
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CCAssignToStack<4, 8>
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]>;
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def CC_MipsN : CallingConv<[
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CCIfType<[i8, i16, i32, i64],
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CCIfSubtargetNot<"isLittle()",
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CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>,
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// First deal with f32s that got turned into i32s due to soft-float
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CCIfType<[i32],
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CCIfSubtarget<"useSoftFloat()",
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CCIfOrigArgWasFloat<CCDelegateTo<CC_MipsN_SoftFloat>>>>,
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// All remaining integers are promoted to 64-bit.
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CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
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// Integer arguments are passed in integer registers.
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CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64,
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T0_64, T1_64, T2_64, T3_64],
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[D12_64, D13_64, D14_64, D15_64,
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D16_64, D17_64, D18_64, D19_64]>>,
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// f32 arguments are passed in single precision FP registers.
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CCIfType<[f32], CCAssignToRegWithShadow<[F12, F13, F14, F15,
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F16, F17, F18, F19],
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[A0_64, A1_64, A2_64, A3_64,
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T0_64, T1_64, T2_64, T3_64]>>,
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// f64 arguments are passed in double precision FP registers.
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CCIfType<[f64], CCAssignToRegWithShadow<[D12_64, D13_64, D14_64, D15_64,
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D16_64, D17_64, D18_64, D19_64],
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[A0_64, A1_64, A2_64, A3_64,
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T0_64, T1_64, T2_64, T3_64]>>,
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// All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
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CCIfType<[f32], CCAssignToStack<4, 8>>,
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CCIfType<[i64, f64], CCAssignToStack<8, 8>>
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]>;
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// N32/64 variable arguments.
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// All arguments are passed in integer registers.
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def CC_MipsN_VarArg : CallingConv<[
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CCIfType<[i8, i16, i32, i64],
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CCIfSubtargetNot<"isLittle()",
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CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>,
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// All integers are promoted to 64-bit.
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CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
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CCIfType<[f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
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CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64,
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T0_64, T1_64, T2_64, T3_64]>>,
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// All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
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CCIfType<[f32], CCAssignToStack<4, 8>>,
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CCIfType<[i64, f64], CCAssignToStack<8, 8>>
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]>;
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def RetCC_MipsN : CallingConv<[
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// f128 needs to be handled similarly to f32 and f64. However, f128 is not
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// legal and is lowered to i128 which is further lowered to a pair of i64's.
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// This presents us with a problem for the calling convention since hard-float
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// still needs to pass them in FPU registers, and soft-float needs to use $v0,
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// and $a0 instead of the usual $v0, and $v1. We therefore resort to a
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// pre-analyze (see PreAnalyzeReturnForF128()) step to pass information on
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// whether the result was originally an f128 into the tablegen-erated code.
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//
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// f128 should only occur for the N64 ABI where long double is 128-bit. On
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// N32, long double is equivalent to double.
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CCIfSubtargetNot<"isSingleFloat()",
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CCIfType<[i64], CCIfOrigArgWasF128<CCDelegateTo<RetCC_F128>>>>,
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// Aggregate returns are positioned at the lowest address in the slot for
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// both little and big-endian targets. When passing in registers, this
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// requires that big-endian targets shift the value into the upper bits.
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CCIfSubtarget<"isLittle()",
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CCIfType<[i8, i16, i32, i64], CCIfInReg<CCPromoteToType<i64>>>>,
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CCIfSubtargetNot<"isLittle()",
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CCIfType<[i8, i16, i32, i64],
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CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>,
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// i64 are returned in registers V0_64, V1_64
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CCIfType<[i64], CCAssignToReg<[V0_64, V1_64]>>,
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// f32 are returned in registers F0, F2
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CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
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// f64 are returned in registers D0, D2
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CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>>
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]>;
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//===----------------------------------------------------------------------===//
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// Mips FastCC Calling Convention
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//===----------------------------------------------------------------------===//
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def CC_MipsO32_FastCC : CallingConv<[
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// f64 arguments are passed in double-precision floating pointer registers.
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CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()",
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CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6,
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D7, D8, D9]>>>,
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CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"useOddSPReg()",
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CCAssignToReg<[D0_64, D1_64, D2_64, D3_64,
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D4_64, D5_64, D6_64, D7_64,
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D8_64, D9_64, D10_64, D11_64,
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D12_64, D13_64, D14_64, D15_64,
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D16_64, D17_64, D18_64,
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D19_64]>>>>,
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CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"noOddSPReg()",
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CCAssignToReg<[D0_64, D2_64, D4_64, D6_64,
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D8_64, D10_64, D12_64, D14_64,
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D16_64, D18_64]>>>>,
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// Stack parameter slots for f64 are 64-bit doublewords and 8-byte aligned.
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CCIfType<[f64], CCAssignToStack<8, 8>>
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]>;
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def CC_MipsN_FastCC : CallingConv<[
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// Integer arguments are passed in integer registers.
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CCIfType<[i64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, T0_64, T1_64,
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T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
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T8_64, V1_64]>>,
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// f64 arguments are passed in double-precision floating pointer registers.
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CCIfType<[f64], CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, D4_64, D5_64,
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D6_64, D7_64, D8_64, D9_64, D10_64, D11_64,
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D12_64, D13_64, D14_64, D15_64, D16_64, D17_64,
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D18_64, D19_64]>>,
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// Stack parameter slots for i64 and f64 are 64-bit doublewords and
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// 8-byte aligned.
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CCIfType<[i64, f64], CCAssignToStack<8, 8>>
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]>;
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def CC_Mips_FastCC : CallingConv<[
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// Handles byval parameters.
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CCIfByVal<CCPassByVal<4, 4>>,
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// Promote i8/i16 arguments to i32.
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CCIfType<[i8, i16], CCPromoteToType<i32>>,
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// Integer arguments are passed in integer registers. All scratch registers,
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// except for AT, V0 and T9, are available to be used as argument registers.
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CCIfType<[i32],
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CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, V1]>>,
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// f32 arguments are passed in single-precision floating pointer registers.
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CCIfType<[f32], CCIfSubtarget<"useOddSPReg()",
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CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13,
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F14, F15, F16, F17, F18, F19]>>>,
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// Don't use odd numbered single-precision registers for -mno-odd-spreg.
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CCIfType<[f32], CCIfSubtarget<"noOddSPReg()",
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CCAssignToReg<[F0, F2, F4, F6, F8, F10, F12, F14, F16, F18]>>>,
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// Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned.
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CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
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CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FastCC>>,
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CCDelegateTo<CC_MipsN_FastCC>
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]>;
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//===----------------------------------------------------------------------===//
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// Mips Calling Convention Dispatch
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//===----------------------------------------------------------------------===//
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def RetCC_Mips : CallingConv<[
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CCIfSubtarget<"isABI_N32()", CCDelegateTo<RetCC_MipsN>>,
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CCIfSubtarget<"isABI_N64()", CCDelegateTo<RetCC_MipsN>>,
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CCDelegateTo<RetCC_MipsO32>
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]>;
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def CC_Mips_ByVal : CallingConv<[
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CCIfSubtarget<"isABI_O32()", CCIfByVal<CCPassByVal<4, 4>>>,
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CCIfByVal<CCPassByVal<8, 8>>
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]>;
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def CC_Mips16RetHelper : CallingConv<[
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CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>,
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// Integer arguments are passed in integer registers.
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CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>
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]>;
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def CC_Mips_FixedArg : CallingConv<[
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// Mips16 needs special handling on some functions.
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CCIf<"State.getCallingConv() != CallingConv::Fast",
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CCIfSpecialCallingConv<"Mips16RetHelperConv",
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CCDelegateTo<CC_Mips16RetHelper>>>,
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CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>,
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// f128 needs to be handled similarly to f32 and f64 on hard-float. However,
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// f128 is not legal and is lowered to i128 which is further lowered to a pair
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// of i64's.
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// This presents us with a problem for the calling convention since hard-float
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// still needs to pass them in FPU registers. We therefore resort to a
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// pre-analyze (see PreAnalyzeFormalArgsForF128()) step to pass information on
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// whether the argument was originally an f128 into the tablegen-erated code.
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//
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// f128 should only occur for the N64 ABI where long double is 128-bit. On
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// N32, long double is equivalent to double.
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CCIfType<[i64],
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CCIfSubtargetNot<"isSingleFloat()",
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CCIfSubtargetNot<"useSoftFloat()",
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CCIfOrigArgWasF128<CCBitConvertToType<f64>>>>>,
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CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_Mips_FastCC>>,
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CCIfSubtarget<"isABI_O32()", CCIfSubtargetNot<"isGP64bit()", CCDelegateTo<CC_MipsO32_FP>>>,
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CCDelegateTo<CC_MipsN>
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]>;
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def CC_Mips_VarArg : CallingConv<[
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CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>,
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CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>,
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CCDelegateTo<CC_MipsN_VarArg>
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]>;
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def CC_Mips : CallingConv<[
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CCIfVarArg<CCIfArgVarArg<CCDelegateTo<CC_Mips_VarArg>>>,
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CCDelegateTo<CC_Mips_FixedArg>
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]>;
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//===----------------------------------------------------------------------===//
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// Callee-saved register lists.
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//===----------------------------------------------------------------------===//
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def CSR_O32_SingleFloat : CalleeSavedRegs<(add(sequence "F%u", 31, 20), RA, FP,
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(sequence "S%u", 7, 0))>;
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def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
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(sequence "S%u", 7, 0))> {
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let OtherPreserved = (add (decimate (sequence "F%u", 30, 20), 2));
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}
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def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
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(sequence "S%u", 7, 0))>;
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def CSR_O32_FP64 :
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CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP,
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(sequence "S%u", 7, 0))>;
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def CSR_N32 : CalleeSavedRegs<(add(decimate(sequence "D%u_64", 30, 20), 2),
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RA_64, FP_64, GP_64, (sequence "S%u_64", 7, 0))>;
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def CSR_N32_SingleFloat
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: CalleeSavedRegs<(add(decimate(sequence "F%u", 30, 20), 2), RA_64, FP_64,
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GP_64, (sequence "S%u_64", 7, 0))>;
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def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64,
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GP_64, (sequence "S%u_64", 7, 0))>;
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def CSR_N64_SingleFloat : CalleeSavedRegs<(add(sequence "F%u", 31, 24), RA_64,
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FP_64, GP_64, (sequence "S%u_64", 7, 0))>;
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def CSR_Mips16RetHelper :
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CalleeSavedRegs<(add V0, V1, FP,
|
|
(sequence "A%u", 3, 0), (sequence "S%u", 7, 0),
|
|
(sequence "D%u", 15, 10))>;
|
|
|
|
def CSR_Interrupt_32R6 : CalleeSavedRegs<(add (sequence "A%u", 3, 0),
|
|
(sequence "S%u", 7, 0),
|
|
(sequence "V%u", 1, 0),
|
|
(sequence "T%u", 9, 0),
|
|
RA, FP, GP, AT)>;
|
|
|
|
def CSR_Interrupt_32 : CalleeSavedRegs<(add (sequence "A%u", 3, 0),
|
|
(sequence "S%u", 7, 0),
|
|
(sequence "V%u", 1, 0),
|
|
(sequence "T%u", 9, 0),
|
|
RA, FP, GP, AT, LO0, HI0)>;
|
|
|
|
def CSR_Interrupt_64R6 : CalleeSavedRegs<(add (sequence "A%u_64", 3, 0),
|
|
(sequence "V%u_64", 1, 0),
|
|
(sequence "S%u_64", 7, 0),
|
|
(sequence "T%u_64", 9, 0),
|
|
RA_64, FP_64, GP_64, AT_64)>;
|
|
|
|
def CSR_Interrupt_64 : CalleeSavedRegs<(add (sequence "A%u_64", 3, 0),
|
|
(sequence "S%u_64", 7, 0),
|
|
(sequence "T%u_64", 9, 0),
|
|
(sequence "V%u_64", 1, 0),
|
|
RA_64, FP_64, GP_64, AT_64,
|
|
LO0_64, HI0_64)>;
|