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llvm-project/llvm/lib/Target/RISCV
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Kai Lin df58c38b5a
[RISCV][DAGCombiner] Fix potential missed combine in VL->VW extension (#168026) 
The previous implementation of `combineOp_VLToVWOp_VL` manually replaced
old
nodes with newly created widened nodes, but only added the new node
itself to
the `DAGCombiner` worklist. Since the users of the new node were not
added,
some combine opportunities could be missed when external `DAGCombiner`
passes
expected those users to be reconsidered.

This patch replaces the custom replacement logic with a call to
`DCI.CombineTo()`, which performs node replacement in a way consistent
with
`DAGCombiner::Run`:
- Replace all uses of the old node.
- Add the new node and its users to the worklist.
- Clean up unused nodes when appropriate.

Using `CombineTo` ensures that `combineOp_VLToVWOp_VL` behaves
consistently with
the standard `DAGCombiner` update model, avoiding discrepancies between
the
private worklist inside this routine and the global worklist managed by
the
combiner.

This resolves missed combine cases involving VL -> VW operator widening.

---------

Co-authored-by: Kai Lin <omg_link@qq.com>
2025-11-19 12:20:22 -08:00
..
AsmParser
[RISCV] Remove Match_InvalidXSfmmVType. NFC (#168465)
2025-11-17 19:05:19 -08:00
Disassembler
[RISCV][MC] Introduce XSfvfexp* and XSfvfbfexpa* extensions and their MC supports (#164349)
2025-10-21 18:27:21 -07:00
GISel
[GISel][RISCV] Compute CTPOP of small odd-sized integer correctly (#168559)
2025-11-18 18:49:13 +00:00
MCA
[Target] Add "override" where appropriate (NFC) (#165083)
2025-10-25 06:23:43 -07:00
MCTargetDesc
[RISCV] Remove implicit conversions of MCRegister to unsigned. NFC (#167588)
2025-11-11 22:32:57 -08:00
TargetInfo
[RISCV] Add initial assembler/MC layer support for big-endian (#146534)
2025-08-22 09:21:10 +02:00
CMakeLists.txt
[RISCV] Introduce pass to promote double constants to a global array (#160536)
2025-11-05 14:31:17 +00:00
RISCV.h
[RISCV][NewPM] Port RISCVCodeGenPrepare to the new pass manager (#168381)
2025-11-19 06:51:18 +00:00
RISCV.td
[RISCV] Implement base scheduling model for andes 45 series processor. (#141008)
2025-06-04 16:11:43 +08:00
RISCVAsmPrinter.cpp
[RISCV] Support XSfmm LLVM IR and CodeGen (#143069)
2025-10-14 02:01:57 +00:00
RISCVCallingConv.cpp
[CodeGen] Provide original IR type to CC lowering (NFC) (#152709)
2025-08-11 08:57:53 +02:00
RISCVCallingConv.h
[CodeGen] Provide original IR type to CC lowering (NFC) (#152709)
2025-08-11 08:57:53 +02:00
RISCVCallingConv.td
[RISCV] Support PreserveMost calling convention (#148214)
2025-07-30 16:30:48 +08:00
RISCVCodeGenPrepare.cpp
[RISCV][NewPM] Port RISCVCodeGenPrepare to the new pass manager (#168381)
2025-11-19 06:51:18 +00:00
RISCVCombine.td
[RISCV][GISel] Fold G_FCONSTANT 0.0 store into G_CONSTANT x0 (#163008)
2025-10-23 15:50:04 +08:00
RISCVConstantPoolValue.cpp
…
RISCVConstantPoolValue.h
[Target] Add "override" where appropriate (NFC) (#165083)
2025-10-25 06:23:43 -07:00
RISCVDeadRegisterDefinitions.cpp
CodeGen: Remove TRI argument from getRegClass (#158225)
2025-11-10 15:43:55 -08:00
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] 'Zalrsc' may permit non-base instructions (#165042)
2025-10-28 12:51:11 -07:00
RISCVExpandPseudoInsts.cpp
[RISCV] Add short forward branch support for lui, qc.li, and qc.e.li (#167481)
2025-11-12 15:47:49 +05:30
RISCVFeatures.td
[RISCV][llvm] Support Smpmpmt version 0.6 (#166322)
2025-11-10 16:09:57 +08:00
RISCVFoldMemOffset.cpp
[RISCV] Clear kill flags after replaceRegWith in RISCVFoldMemOffset. (#136762)
2025-04-22 19:24:29 -07:00
RISCVFrameLowering.cpp
[RISCV] Add an option to enable CFIInstrInserter. (#164477)
2025-11-18 02:46:43 -05:00
RISCVFrameLowering.h
[RISCV] Add an option to enable CFIInstrInserter. (#164477)
2025-11-18 02:46:43 -05:00
RISCVGatherScatterLowering.cpp
[IR] Replace alignment argument with attribute on masked intrinsics (#163802)
2025-10-20 08:50:09 +00:00
RISCVGISel.td
[RISCV][GISel] Add manual isel for s8/s16/s32 load/store for the GPR bank. (#161995)
2025-10-07 21:30:09 -07:00
RISCVIndirectBranchTracking.cpp
[RISCV][NFC] Fix typo in RISCVIndirectBranchTracking.cpp (#157221)
2025-09-08 15:02:48 +08:00
RISCVInsertReadWriteCSR.cpp
…
RISCVInsertVSETVLI.cpp
[RISCV] Fix RISCVInsertVSETVLI coalescing clobbering VL def segment (#167712)
2025-11-13 09:11:19 +00:00
RISCVInsertWriteVXRM.cpp
[llvm] Use "= default" (NFC) (#166088)
2025-11-02 17:16:47 -08:00
RISCVInstrFormats.td
[RISCV] Use a tablegen class for AltFmtType. NFC (#163251)
2025-10-13 23:19:23 -07:00
RISCVInstrFormatsC.td
[RISCV] Remove post-decoding instruction adjustments (#156360)
2025-09-04 16:02:34 +00:00
RISCVInstrFormatsV.td
…
RISCVInstrGISel.td
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVInstrInfo.cpp
[RISCV] Add short forward branch support for lui, qc.li, and qc.e.li (#167481)
2025-11-12 15:47:49 +05:30
RISCVInstrInfo.h
CodeGen: Remove TRI arguments from stack load/store hooks (#158240)
2025-11-10 16:24:39 -08:00
RISCVInstrInfo.td
[RISCV] Mask integer and float loads as canFoldAsLoad for stackmaps (#165761)
2025-10-31 14:42:16 +00:00
RISCVInstrInfoA.td
[RISCV][LLVM] Enable atomics for 'Zalrsc' (#163672)
2025-10-21 09:33:19 -07:00
RISCVInstrInfoC.td
[TableGen][DecoderEmitter][RISCV] Always handle bits<0> (#159951)
2025-09-22 20:50:17 +03:00
RISCVInstrInfoD.td
[RISCV] Mask integer and float loads as canFoldAsLoad for stackmaps (#165761)
2025-10-31 14:42:16 +00:00
RISCVInstrInfoF.td
[RISCV] Mask integer and float loads as canFoldAsLoad for stackmaps (#165761)
2025-10-31 14:42:16 +00:00
RISCVInstrInfoM.td
[RISCV][NFC] Cleanup Negative Predicate Names (#155017)
2025-08-22 14:46:41 -07:00
RISCVInstrInfoP.td
[llvm][RISCV] Support P extension CodeGen (#167882)
2025-11-14 07:48:37 +00:00
RISCVInstrInfoQ.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVInstrInfoSFB.td
[RISCV] Add short forward branch support for lui, qc.li, and qc.e.li (#167481)
2025-11-12 15:47:49 +05:30
RISCVInstrInfoV.td
[NFC][RISCV] Move Zvfbf* relative stuffs to RISCVInstrInfoZvfbf.td (#159619)
2025-09-19 23:57:59 +08:00
RISCVInstrInfoVPseudos.td
[RISCV] Move more stuff to RISCVInstrInfoZvfbf.td. Fix incorrect Predicates. (#163846)
2025-10-16 21:26:34 -07:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Rename BFloatVectors -> BF16Vectors in tablegen. NFC (#161469)
2025-09-30 19:53:21 -07:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Rename BFloatVectors -> BF16Vectors in tablegen. NFC (#161469)
2025-09-30 19:53:21 -07:00
RISCVInstrInfoXAndes.td
[RISCV] Rename BFloatVectors -> BF16Vectors in tablegen. NFC (#161469)
2025-09-30 19:53:21 -07:00
RISCVInstrInfoXCV.td
[RISCV] Use i32 in more RV32 only patterns. NFC
2025-10-11 09:57:10 -07:00
RISCVInstrInfoXMips.td
[RISCV] Add "MIPS" to name of MIPS-specific RISCVSubtarget functions. NFC (#162122)
2025-10-06 11:33:20 -07:00
RISCVInstrInfoXqccmp.td
…
RISCVInstrInfoXqci.td
[RISCV] Add short forward branch support for lui, qc.li, and qc.e.li (#167481)
2025-11-12 15:47:49 +05:30
RISCVInstrInfoXRivos.td
[RISCV] Add TSFlag for reading past VL behaviour. NFCI (#149704)
2025-08-15 01:19:03 +00:00
RISCVInstrInfoXSf.td
[RISCV] Add LLVM IR intrinsics and codegen for XSfvfexp* and XSfvfexpa* (#164499)
2025-10-24 18:09:03 +00:00
RISCVInstrInfoXSfmm.td
[RISCV] Remove Match_InvalidXSfmmVType. NFC (#168465)
2025-11-17 19:05:19 -08:00
RISCVInstrInfoXSpacemiT.td
[RISCV] Fold argstr into class for XSMTVDot instructions. NFC.
2025-08-21 13:12:46 +08:00
RISCVInstrInfoXTHead.td
[RISCV] Use TargetConstant for the immediate RISCVISD::SHL_ADD nodes. (#166312)
2025-11-04 09:56:59 -08:00
RISCVInstrInfoXVentana.td
…
RISCVInstrInfoXwch.td
[RISCV] Remove post-decoding instruction adjustments (#156360)
2025-09-04 16:02:34 +00:00
RISCVInstrInfoZa.td
[RISCV] Reorder ins/outs of atomic instruction to match their assembly order. NFC (#162411)
2025-10-07 22:24:52 -07:00
RISCVInstrInfoZalasr.td
[RISCV][GISel] Add manual isel for s8/s16/s32 load/store for the GPR bank. (#161995)
2025-10-07 21:30:09 -07:00
RISCVInstrInfoZb.td
[RISCV] Support codegen for some scalar P extension instructions. (#164359)
2025-10-24 18:20:53 +00:00
RISCVInstrInfoZc.td
[RISCV] Remove extra operands from Zcb compression patterns. NFC (#150541)
2025-07-24 18:03:30 -07:00
RISCVInstrInfoZclsd.td
…
RISCVInstrInfoZcmop.td
[RISCV] Add underscores to instructions names for Zimop/Zcmop. (#155289)
2025-08-25 14:06:28 -07:00
RISCVInstrInfoZfa.td
[RISCV] Fix schedule info for FMVP_D_X. (#140766)
2025-05-22 08:39:57 -07:00
RISCVInstrInfoZfbfmin.td
[RISCV] Add isel for bitcasting between bfloat and half types (#158828)
2025-09-17 12:10:47 -07:00
RISCVInstrInfoZfh.td
[RISCV] Mark FLH as canFoldAsLoad. (#165974)
2025-11-03 12:35:06 -08:00
RISCVInstrInfoZibi.td
[RISCV][CodeGen] Add CodeGen support of Zibi experimental extension (#146858)
2025-09-18 11:03:48 +08:00
RISCVInstrInfoZicbo.td
[RISCV][NFC] Cleanup Negative Predicate Names (#155017)
2025-08-22 14:46:41 -07:00
RISCVInstrInfoZicfiss.td
[RISCV] Remove a couple of custom instruction decoders (NFC) (#158483)
2025-09-15 00:57:31 +03:00
RISCVInstrInfoZicond.td
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVInstrInfoZilsd.td
[RISCV] Lower i64 load/stores to ld/sd with Zilsd. (#139808)
2025-05-14 09:54:07 -07:00
RISCVInstrInfoZimop.td
[RISCV] Add underscores to instructions names for Zimop/Zcmop. (#155289)
2025-08-25 14:06:28 -07:00
RISCVInstrInfoZk.td
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVInstrInfoZvfbf.td
[llvm][RISCV] Support Zvfbfa codegen for fneg, fabs and copysign (#166944)
2025-11-10 04:06:17 +00:00
RISCVInstrInfoZvfofp8min.td
[RISCV] Implement MC support for Zvfofp8min extension (#157014)
2025-09-19 07:49:31 +00:00
RISCVInstrInfoZvk.td
[RISCV] Remove duplicate vsha2ch/vsha2cl/vsha2ms i32 patterns. NFC (#151835)
2025-08-02 21:53:58 -07:00
RISCVInstrInfoZvqdotq.td
[RISCV] Support ZVqdot Codegen and C intrinsics (#154915)
2025-09-05 11:38:58 +08:00
RISCVInstrPredicates.td
[RISCV] Add XSfmm pseudo instruction and vset* insertion support (#143068)
2025-10-13 15:06:31 +00:00
RISCVInterleavedAccess.cpp
[IR] Replace alignment argument with attribute on masked intrinsics (#163802)
2025-10-20 08:50:09 +00:00
RISCVISelDAGToDAG.cpp
[RISCV] Remove custom legalization of v2i16/v4i8 loads for P extension. (#167651)
2025-11-12 19:32:06 -08:00
RISCVISelDAGToDAG.h
[RISCV] Support XSfmm LLVM IR and CodeGen (#143069)
2025-10-14 02:01:57 +00:00
RISCVISelLowering.cpp
[RISCV][DAGCombiner] Fix potential missed combine in VL->VW extension (#168026)
2025-11-19 12:20:22 -08:00
RISCVISelLowering.h
[RISCV] Legalize misaligned unmasked vp.load/vp.store to vle8/vse8. (#167745)
2025-11-18 11:13:54 -08:00
RISCVLandingPadSetup.cpp
…
RISCVLateBranchOpt.cpp
[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762)
2025-06-25 23:09:24 -07:00
RISCVLoadStoreOptimizer.cpp
[RISCV] Add "MIPS" to name of MIPS-specific RISCVSubtarget functions. NFC (#162122)
2025-10-06 11:33:20 -07:00
RISCVMachineFunctionInfo.cpp
[RISCV] SiFive CLIC Support (#132481)
2025-04-25 17:12:27 -07:00
RISCVMachineFunctionInfo.h
[Target] Add "override" where appropriate (NFC) (#165083)
2025-10-25 06:23:43 -07:00
RISCVMacroFusion.td
[RISCV] add more generic macrofusions (#151140)
2025-08-06 14:46:34 -04:00
RISCVMakeCompressible.cpp
[RISCV] Replace uses of RISCV::NoRegister with Register() or isValid. NFC (#161781)
2025-10-03 08:53:58 -07:00
RISCVMergeBaseOffset.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
RISCVMoveMerger.cpp
[RISCV] Minor refactor of RISCVMoveMerge::mergePairedInsns. (#154467)
2025-08-20 09:07:58 -07:00
RISCVOptWInstrs.cpp
[RISCV] Support P extension ABSW instruction. (#165047)
2025-10-30 08:42:38 -07:00
RISCVPassRegistry.def
[RISCV][NewPM] Port RISCVCodeGenPrepare to the new pass manager (#168381)
2025-11-19 06:51:18 +00:00
RISCVPfmCounters.td
…
RISCVPostRAExpandPseudoInsts.cpp
…
RISCVProcessors.td
[RISCV] Toggle throttled FP64 feature in SiFive7 scheduling model with subtarget feature (#162400)
2025-10-10 01:26:17 +00:00
RISCVProfiles.td
[RISCV][NFC] Add Zicsr to profiles explicitly (#136134)
2025-04-18 10:59:32 +08:00
RISCVPromoteConstant.cpp
[RISCV] Introduce pass to promote double constants to a global array (#160536)
2025-11-05 14:31:17 +00:00
RISCVPushPopOptimizer.cpp
…
RISCVRedundantCopyElimination.cpp
[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762)
2025-06-25 23:09:24 -07:00
RISCVRegisterInfo.cpp
[RISCV] Reduce number of GPRs needed by lowerSegmentSpillReload. (#165337)
2025-10-31 10:05:14 -07:00
RISCVRegisterInfo.h
CodeGen: Remove MachineFunction argument from getPointerRegClass (#158185)
2025-09-12 09:18:50 +00:00
RISCVRegisterInfo.td
[RISCV][llvm] Preliminary P extension codegen support (#162668)
2025-11-11 17:01:45 +08:00
RISCVSchedAndes45.td
[RISCV] Fix typo in comment Interger->Integer. NFC
2025-08-13 11:19:49 -07:00
RISCVSchedGenericOOO.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedMIPSP8700.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedRocket.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSiFive7.td
[RISCV] Add LLVM IR intrinsics and codegen for XSfvfexp* and XSfvfexpa* (#164499)
2025-10-24 18:09:03 +00:00
RISCVSchedSiFiveP400.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSiFiveP500.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSiFiveP600.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSiFiveP800.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSpacemitX60.td
[RISCV] Update X60 ReleaseAtCycles for Vector Integer Arithmetic Instructions (#152557)
2025-11-19 14:53:20 -03:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSyntacoreSCR7.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedSyntacoreSCR345.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedTTAscalonD8.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSchedule.td
[RISCV] Add LLVM IR intrinsics and codegen for XSfvfexp* and XSfvfexpa* (#164499)
2025-10-24 18:09:03 +00:00
RISCVScheduleV.td
[RISCV] Toggle throttled FP64 feature in SiFive7 scheduling model with subtarget feature (#162400)
2025-10-10 01:26:17 +00:00
RISCVScheduleXSf.td
[RISCV] Add LLVM IR intrinsics and codegen for XSfvfexp* and XSfvfexpa* (#164499)
2025-10-24 18:09:03 +00:00
RISCVScheduleZb.td
…
RISCVScheduleZvk.td
…
RISCVSchedXiangShanNanHu.td
[RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666)
2025-07-10 14:15:22 +08:00
RISCVSelectionDAGInfo.cpp
[SelectionDAG] Verify SDTCisVT and SDTCVecEltisVT constraints (#150125)
2025-11-16 18:26:03 +03:00
RISCVSelectionDAGInfo.h
[RISCV] Implement EmitTargetCodeForMemset for Xqcilsm (#151555)
2025-08-04 12:51:14 +05:30
RISCVSubtarget.cpp
[RISCV] Convert -mtune=generic to generic-rv32/rv64 in RISCVSubtarget::initializeSubtargetDependencies. (#168612)
2025-11-19 00:08:24 -08:00
RISCVSubtarget.h
CodeGen: Remove target hook for terminal rule (#165962)
2025-11-12 21:12:19 +00:00
RISCVSystemOperands.td
[RISCV] Sort RISCVSystemOperands to match the RISC-V Privilege Specification. (#140967)
2025-05-22 08:46:48 -07:00
RISCVTargetMachine.cpp
[RISCV][NewPM] Port RISCVCodeGenPrepare to the new pass manager (#168381)
2025-11-19 06:51:18 +00:00
RISCVTargetMachine.h
…
RISCVTargetObjectFile.cpp
RISCV: Replace RISCVMCExpr with MCSpecifierExpr
2025-06-15 16:51:09 -07:00
RISCVTargetObjectFile.h
RISCV: Replace RISCVMCExpr with MCSpecifierExpr
2025-06-15 16:51:09 -07:00
RISCVTargetTransformInfo.cpp
[TTI] Use MemIntrinsicCostAttributes for getMaskedMemoryOpCost (#168029)
2025-11-19 09:51:12 +08:00
RISCVTargetTransformInfo.h
[TTI] Use MemIntrinsicCostAttributes for getMaskedMemoryOpCost (#168029)
2025-11-19 09:51:12 +08:00
RISCVVectorMaskDAGMutation.cpp
Reland "[RISCV] AddEdge between mask producer and user of V0 (#146855)" (#148566)
2025-07-18 10:56:07 +08:00
RISCVVectorPeephole.cpp
CodeGen: Remove TRI argument from getRegClass (#158225)
2025-11-10 15:43:55 -08:00
RISCVVLOptimizer.cpp
[RISCV] Reduce minimum VL needed for vslidedown.vx in RISCVVLOptimizer (#168392)
2025-11-18 06:38:55 +00:00
RISCVVMV0Elimination.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
RISCVZacasABIFix.cpp
…