d219467cd8
Add a 64-bit feature so a subtarget feature check can tell the pointer size, for future use with HwMode. This is kind of a hack, but this is closer to what other targets do. To use HwModes, there needs to be a subtarget feature. Every other target kludges the module level properties into a subtarget feature for use here, which requires pre/post processing the subtarget features. The APIs for this aren't great. I tried doing something different, closer to what hexagon does, rather than what x86 does to see if it was any nicer. It almost is, except for some reason we don't have an API to directly set a bit in the FeatureBitset. Also the test coverage for the different ABI options isn't great. e.g. v9 as a feature almost works, except a single test breaks that uses a sparc32 triple with an explicit v9 feature.
100 lines
3.2 KiB
C++
100 lines
3.2 KiB
C++
//===-- SparcSubtarget.cpp - SPARC Subtarget Information ------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the SPARC specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcSubtarget.h"
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#include "SparcSelectionDAGInfo.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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#define DEBUG_TYPE "sparc-subtarget"
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "SparcGenSubtargetInfo.inc"
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void SparcSubtarget::anchor() { }
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SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(
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StringRef CPU, StringRef TuneCPU, StringRef FS) {
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const Triple &TT = getTargetTriple();
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// Determine default and user specified characteristics
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std::string CPUName = std::string(CPU);
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if (CPUName.empty())
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CPUName = TT.isSPARC64() ? "v9" : "v8";
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if (TuneCPU.empty())
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TuneCPU = CPUName;
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// Parse features string.
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ParseSubtargetFeatures(CPUName, TuneCPU, FS);
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if (!Is64Bit && TT.isSPARC64()) {
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FeatureBitset Features = getFeatureBits();
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setFeatureBits(Features.set(Sparc::Feature64Bit));
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Is64Bit = true;
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}
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// Popc is a v9-only instruction.
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if (!IsV9)
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UsePopc = false;
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return *this;
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}
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SparcSubtarget::SparcSubtarget(const StringRef &CPU, const StringRef &TuneCPU,
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const StringRef &FS, const TargetMachine &TM)
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: SparcGenSubtargetInfo(TM.getTargetTriple(), CPU, TuneCPU, FS),
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ReserveRegister(TM.getMCRegisterInfo()->getNumRegs()),
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InstrInfo(initializeSubtargetDependencies(CPU, TuneCPU, FS)),
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TLInfo(TM, *this), FrameLowering(*this) {
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TSInfo = std::make_unique<SparcSelectionDAGInfo>();
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}
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SparcSubtarget::~SparcSubtarget() = default;
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const SelectionDAGTargetInfo *SparcSubtarget::getSelectionDAGInfo() const {
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return TSInfo.get();
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}
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int SparcSubtarget::getAdjustedFrameSize(int frameSize) const {
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if (is64Bit()) {
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// All 64-bit stack frames must be 16-byte aligned, and must reserve space
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// for spilling the 16 window registers at %sp+BIAS..%sp+BIAS+128.
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frameSize += 128;
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// Frames with calls must also reserve space for 6 outgoing arguments
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// whether they are used or not. LowerCall_64 takes care of that.
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frameSize = alignTo(frameSize, 16);
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} else {
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// Emit the correct save instruction based on the number of bytes in
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// the frame. Minimum stack frame size according to V8 ABI is:
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// 16 words for register window spill
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// 1 word for address of returned aggregate-value
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// + 6 words for passing parameters on the stack
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// ----------
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// 23 words * 4 bytes per word = 92 bytes
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frameSize += 92;
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// Round up to next doubleword boundary -- a double-word boundary
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// is required by the ABI.
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frameSize = alignTo(frameSize, 8);
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}
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return frameSize;
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}
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bool SparcSubtarget::enableMachineScheduler() const {
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return true;
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}
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