9811226967
This allows removing a special case hack in ARM. ARM's implementation of getExtractSubregLikeInputs has the strange property that it reports a register with a class that does not support the reported subregister index. We can however reconstrain the register to support this usage. This is an alternative to #159600. I've included the test, but the output is different. In this case version the VMOVSR is replaced with an ordinary subregister extract copy.
29 lines
1.0 KiB
LLVM
29 lines
1.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=arm-none-eabihf -mcpu=cortex-a55 < %s | FileCheck %s
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; Test that the override of shouldRewriteCopySrc does something
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define float @shouldRewriteCopySrc(double %arg) #0 {
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; CHECK-LABEL: shouldRewriteCopySrc:
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; CHECK: @ %bb.0: @ %bb
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; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: vadd.f64 d16, d0, d0
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; CHECK-NEXT: @APP
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; CHECK-NEXT: nop
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; CHECK-NEXT: @NO_APP
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; CHECK-NEXT: vmov.f64 d0, d16
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; CHECK-NEXT: @ kill: def $s0 killed $s0 killed $d0
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; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: bx lr
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bb:
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%i = fadd double %arg, %arg
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tail call void asm sideeffect "nop", "~{q0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7}"() #0
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%i1 = bitcast double %i to i64
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%i2 = trunc i64 %i1 to i32
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%i3 = bitcast i32 %i2 to float
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ret float %i3
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}
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attributes #0 = { nounwind }
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