f76921ac0d
Tests have been regenerated to favour UTC-emitted lines. While this may not be strictly necessary – as the final migration to MemorySSA should boil down to a simple flip –, adopting UTC-based lines should overall make tests more robust as well as easier to diff (at least on the majority of the tests instances where the new lines have been added). Crash tests now feature check lines as well (notably, pr17852.ll, pr24397.ll and unreachable_block_infinite_loop.ll). Pre-2010 tests leveraging llvm-dis have not been updated.
23 lines
712 B
LLVM
23 lines
712 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
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; RUN: opt -passes=gvn -S < %s | FileCheck %s
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target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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; RLE over the second load.
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define i32 @main(ptr %foo) {
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; CHECK-LABEL: define i32 @main(
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; CHECK-SAME: ptr [[FOO:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[FOO]], align 4
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; CHECK-NEXT: store i32 5, ptr undef, align 4
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; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], [[TMP0]]
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; CHECK-NEXT: ret i32 [[TMP1]]
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;
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entry:
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%0 = load i32, ptr %foo, align 4
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store i32 5, ptr undef, align 4
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%1 = load i32, ptr %foo, align 4
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%2 = add i32 %0, %1
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ret i32 %2
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}
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