573ca36753
The `masked.load`, `masked.store`, `masked.gather` and `masked.scatter` intrinsics currently accept a separate alignment immarg. Replace this with an `align` attribute on the pointer / vector of pointers argument. This is the standard representation for alignment information on intrinsics, and is already used by all other memory intrinsics. This means the signatures now match llvm.expandload, llvm.vp.load, etc. (Things like llvm.memcpy used to have a separate alignment argument as well, but were already migrated a long time ago.) It's worth noting that the masked.gather and masked.scatter intrinsics previously accepted a zero alignment to indicate the ABI type alignment of the element type. This special case is gone now: If the align attribute is omitted, the implied alignment is 1, as usual. If ABI alignment is desired, it needs to be explicitly emitted (which the IRBuilder API already requires anyway).
47 lines
2.1 KiB
LLVM
47 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt < %s -passes=infer-alignment -S | FileCheck %s
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define <2 x i32> @load(<2 x i1> %mask, ptr %ptr) {
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; CHECK-LABEL: define <2 x i32> @load(
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; CHECK-SAME: <2 x i1> [[MASK:%.*]], ptr [[PTR:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[PTR]], i64 64) ]
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; CHECK-NEXT: [[MASKED_LOAD:%.*]] = call <2 x i32> @llvm.masked.load.v2i32.p0(ptr align 64 [[PTR]], <2 x i1> [[MASK]], <2 x i32> poison)
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; CHECK-NEXT: ret <2 x i32> [[MASKED_LOAD]]
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;
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entry:
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call void @llvm.assume(i1 true) [ "align"(ptr %ptr, i64 64) ]
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%masked_load = call <2 x i32> @llvm.masked.load.v2i32.p0(ptr %ptr, i32 1, <2 x i1> %mask, <2 x i32> poison)
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ret <2 x i32> %masked_load
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}
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define void @store(<2 x i1> %mask, <2 x i32> %val, ptr %ptr) {
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; CHECK-LABEL: define void @store(
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; CHECK-SAME: <2 x i1> [[MASK:%.*]], <2 x i32> [[VAL:%.*]], ptr [[PTR:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[PTR]], i64 64) ]
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; CHECK-NEXT: tail call void @llvm.masked.store.v2i32.p0(<2 x i32> [[VAL]], ptr align 64 [[PTR]], <2 x i1> [[MASK]])
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; CHECK-NEXT: ret void
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;
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entry:
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call void @llvm.assume(i1 true) [ "align"(ptr %ptr, i64 64) ]
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tail call void @llvm.masked.store.v2i32.p0(<2 x i32> %val, ptr %ptr, i32 1, <2 x i1> %mask)
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ret void
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}
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define <2 x i32> @null(<2 x i1> %mask, <2 x i32> %val) {
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; CHECK-LABEL: define <2 x i32> @null(
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; CHECK-SAME: <2 x i1> [[MASK:%.*]], <2 x i32> [[VAL:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[MASKED_LOAD:%.*]] = tail call <2 x i32> @llvm.masked.load.v2i32.p0(ptr align 4294967296 null, <2 x i1> [[MASK]], <2 x i32> [[VAL]])
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; CHECK-NEXT: ret <2 x i32> [[MASKED_LOAD]]
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;
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entry:
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%masked_load = tail call <2 x i32> @llvm.masked.load.v2i32.p0(ptr null, i32 1, <2 x i1> %mask, <2 x i32> %val)
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ret <2 x i32> %masked_load
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}
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declare void @llvm.assume(i1)
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declare <2 x i32> @llvm.masked.load.v2i32.p0(ptr, i32, <2 x i1>, <2 x i32>)
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declare void @llvm.masked.store.v2i32.p0(<2 x i32>, ptr, i32, <2 x i1>)
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