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llvm-project/llvm/test/Transforms/LoopVectorize/RISCV
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Florian Hahn 7c34848ae1
[VPlan] Hoist loads with invariant addresses using noalias metadata. (#166247) 
This patch implements a transform to hoists single-scalar replicated
loads with invariant addresses out of the vector loop to the preheader
when scoped noalias metadata proves they cannot alias with any stores in
the loop.

This enables hosting of loads we can prove do not alias any stores in
the loop due to memory runtime checks added during vectorization.

PR: https://github.com/llvm/llvm-project/pull/166247
2025-11-18 09:35:48 +00:00
..
bf16.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
blend-any-of-reduction-cost.ll
[RISCV] Enable tail folding by default (#151681)
2025-08-08 14:26:23 +08:00
blocks-with-dead-instructions.ll
Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)
2025-11-17 13:44:25 +00:00
dead-ops-cost.ll
Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)
2025-11-17 13:44:25 +00:00
defaults.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
divrem.ll
Revert "[LV] Use ExtractLane(LastActiveLane, V) live outs when tail-folding. (#149042)"
2025-11-13 22:34:55 +00:00
evl-compatible-loops.ll
Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)
2025-11-17 13:44:25 +00:00
f16.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
first-order-recurrence-scalable-vf1.ll
Revert "[LV] Use ExtractLane(LastActiveLane, V) live outs when tail-folding. (#149042)"
2025-11-13 22:34:55 +00:00
fminimumnum.ll
[LV][EVL] Remove metadata on EVL vectorized loops (#155760)
2025-09-23 07:39:33 +08:00
force-vect-msg.ll
[LV][RISCV] Try fixing Windows buildbot failure in force-vect-msg.ll. NFC
2025-08-09 21:09:36 +08:00
gather-scatter-cost.ll
Revert "[VPlan] Handle WidenGEP in narrowToSingleScalars" (#167509)
2025-11-11 14:29:28 +00:00
illegal-type.ll
…
induction-costs.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
inloop-reduction.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
interleaved-accesses-zve32x.ll
…
interleaved-accesses.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
interleaved-cost.ll
[RISCV] Enable tail folding by default (#151681)
2025-08-08 14:26:23 +08:00
interleaved-masked-access.ll
Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)
2025-11-17 13:44:25 +00:00
interleaved-store-with-gap.ll
Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)
2025-11-17 13:44:25 +00:00
lit.local.cfg
…
lmul.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
low-trip-count.ll
[VPlan] Simplify ExplicitVectorLength(%AVL) -> %AVL when AVL <= VF (#167647)
2025-11-13 13:17:01 +00:00
mask-index-type.ll
Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)
2025-11-17 13:44:25 +00:00
masked_gather_scatter.ll
Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)
2025-11-17 13:44:25 +00:00
only-compute-cost-for-vplan-vfs.ll
[VPlan] Support VPWidenPointerInductionRecipes with EVL tail folding (#152110)
2025-08-07 10:54:24 +08:00
ordered-reduction.ll
[VPlan] Remove VPVectorPointer for part 0 after unrolling. (#149735)
2025-07-27 13:53:26 +01:00
partial-reduce-dot-product.ll
[VPlan] Disable partial reductions again with EVL tail folding (#167863)
2025-11-14 06:30:12 +00:00
pointer-induction.ll
Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)
2025-11-17 13:44:25 +00:00
pr87378-vpinstruction-or-drop-poison-generating-flags.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
pr88802.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
pr154103.ll
[Reland] "[RISCV][TTI] Implement getAddressComputationCost() in RISCV TTI. #149955" (#156386)
2025-09-02 11:43:27 +08:00
preserve-dbg-loc.ll
[RISCV][LV] Use predicate-else-scalar-epilogue flag in tail folding tests. NFC
2025-07-28 17:04:00 +08:00
reductions.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
reg-usage-bf16.ll
[VPlan] Always consider register pressure on RISC-V (#156951)
2025-09-12 06:21:54 +00:00
reg-usage-f16.ll
[VPlan] Always consider register pressure on RISC-V (#156951)
2025-09-12 06:21:54 +00:00
reg-usage-maxbandwidth.ll
[LV][VPlan] Reduce register usage of VPEVLBasedIVPHIRecipe. (#154482)
2025-08-21 07:39:01 +08:00
reg-usage-prune-vf.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
reg-usage.ll
[VPlan] Always consider register pressure on RISC-V (#156951)
2025-09-12 06:21:54 +00:00
remark-reductions.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
riscv-interleaved.ll
…
riscv-unroll.ll
[VPlan] Remove VPVectorPointer for part 0 after unrolling. (#149735)
2025-07-27 13:53:26 +01:00
riscv-vector-reverse.ll
[VPlan] Add VPInstruction to unpack vector values to scalars. (#155670)
2025-10-19 18:49:05 +00:00
safe-dep-distance.ll
Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)
2025-11-17 13:44:25 +00:00
scalable-basics.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
scalable-tailfold.ll
Revert "[LV] Use ExtractLane(LastActiveLane, V) live outs when tail-folding. (#149042)"
2025-11-13 22:34:55 +00:00
scalable-vf-hint.ll
…
select-cmp-reduction.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
select-invariant-cond-cost.ll
…
short-trip-count.ll
[RISCV] Enable tail folding by default (#151681)
2025-08-08 14:26:23 +08:00
strided-accesses.ll
Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)
2025-11-17 13:44:25 +00:00
tail-folding-bin-unary-ops-args.ll
[LV][EVL] Remove metadata on EVL vectorized loops (#155760)
2025-09-23 07:39:33 +08:00
tail-folding-call-intrinsics.ll
[LV][EVL] Remove metadata on EVL vectorized loops (#155760)
2025-09-23 07:39:33 +08:00
tail-folding-cast-intrinsics.ll
Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)
2025-11-17 13:44:25 +00:00
tail-folding-cond-reduction.ll
Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)
2025-11-17 13:44:25 +00:00
tail-folding-cost.ll
[RISCV][LV] Remove redundant -force-tail-folding-style from tests. NFC
2025-07-28 16:11:01 +08:00
tail-folding-div.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
tail-folding-fixed-order-recurrence.ll
Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)
2025-11-17 13:44:25 +00:00
tail-folding-gather-scatter.ll
[Reland] "[RISCV][TTI] Implement getAddressComputationCost() in RISCV TTI. #149955" (#156386)
2025-09-02 11:43:27 +08:00
tail-folding-inloop-reduction.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
tail-folding-interleave.ll
Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)
2025-11-17 13:44:25 +00:00
tail-folding-intermediate-store.ll
[LV][EVL] Remove metadata on EVL vectorized loops (#155760)
2025-09-23 07:39:33 +08:00
tail-folding-iv32.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
tail-folding-known-no-overflow.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
tail-folding-masked-loadstore.ll
[IR] Replace alignment argument with attribute on masked intrinsics (#163802)
2025-10-20 08:50:09 +00:00
tail-folding-no-masking.ll
[RISCV][LV] Use predicate-else-scalar-epilogue flag in tail folding tests. NFC
2025-07-28 17:04:00 +08:00
tail-folding-ordered-reduction.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
tail-folding-reduction-cost.ll
[RISCV][LV] Use predicate-else-scalar-epilogue flag in tail folding tests. NFC
2025-07-28 17:04:00 +08:00
tail-folding-reduction.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
tail-folding-reverse-load-store.ll
[IR] Replace alignment argument with attribute on masked intrinsics (#163802)
2025-10-20 08:50:09 +00:00
tail-folding-safe-dep-distance.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
tail-folding-uniform-store.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
transform-narrow-interleave-to-widen-memory.ll
[VPlan] Plumb scalable register size through narrowInterleaveGroups (#167505)
2025-11-12 11:14:53 +00:00
truncate-to-minimal-bitwidth-cost.ll
[LV] Check for TruncInsts in canTruncateToMinimalBitwidth.
2025-10-20 22:31:16 +01:00
truncate-to-minimal-bitwidth-evl-crash.ll
[VPlan] Set flags when constructing truncs using VPWidenCastRecipe.
2025-10-12 14:01:12 +01:00
type-info-cache-evl-crash.ll
[LV][EVL] Remove metadata on EVL vectorized loops (#155760)
2025-09-23 07:39:33 +08:00
uniform-load-store.ll
Reland [VPlan] Expand WidenInt inductions with nuw/nsw (#168354)
2025-11-17 13:44:25 +00:00
unroll-in-loop-vectorizer.ll
…
veclib-function-calls.ll
[IR] Mark vector intrinsics speculatable (#162334)
2025-10-09 09:41:59 +01:00
vector-loop-backedge-elimination-with-evl.ll
[VPlan] Simplify ExplicitVectorLength(%AVL) -> %AVL when AVL <= VF (#167647)
2025-11-13 13:17:01 +00:00
vectorize-vp-intrinsics.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
vf-will-not-generate-any-vector-insts.ll
[VPlan] Hoist loads with invariant addresses using noalias metadata. (#166247)
2025-11-18 09:35:48 +00:00
vplan-riscv-vector-reverse.ll
[RISCV] Enable tail folding by default (#151681)
2025-08-08 14:26:23 +08:00
vplan-vp-intrinsics-fixed-order-recurrence.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
vplan-vp-intrinsics-reduction.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
vplan-vp-intrinsics.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
zvl32b.ll
…