Kunqiu Chen 511c9c0648
[UTC] Support to test annotated IR (#165419)
Some analysis/transformation, e.g., predicate info/ mem ssa, insert
instruction annotations as comments, referring to
https://github.com/llvm/llvm-project/pull/165249#discussion_r2466200672.

This PR makes UTC support checking these instruction annotations with an
extra UTC option `-check-inst-comments`.

E.g., 
Before:
```LLVM
; CHECK:         [[Z_0:%.*]] = bitcast i1 [[Z]] to i1
```
After:
```LLVM
; CHECK-NEXT:  ; branch predicate info { TrueEdge: 0 Comparison: [[Z]] = and i1 [[XZ]], [[YZ]] Edge: [label [[TMP0:%.*]],label %nope], RenamedOp: [[Z]] }
; CHECK-NEXT:    [[Z_0:%.*]] = bitcast i1 [[Z]] to i1
```

This PR also regenerates all UTC-generated tests for PredicateInfo; No
MemSSA test is updated, as there are no UTC-generated tests designated
for `print<memoryssa>`.
2025-10-31 21:04:35 +08:00
..