Jianhui Li 9dc4ebfff1

[MLIR][XeGPU] Allow create mem desc from 2d memref (#167767) ...

This PR relax the create_mem_desc's restriction on source memref,
allowing it to be a 2d memref.

2025-11-18 21:31:17 -08:00

..

create_nd_tdesc.mlir

[MLIR][Conversion] XeGPU to XeVM: Add handler for 1D block ops (#165894)

2025-11-10 09:02:32 -08:00

dpas.mlir

[MLIR][XeGPU] XeVM lowering support for load_matrix/store_matrix + fix sanitizer issue (#163858)

2025-10-16 14:09:48 -07:00

fence.mlir

…

loadstore_1d.mlir

[MLIR][Conversion] XeGPU to XeVM: Add handler for 1D block ops (#165894)

2025-11-10 09:02:32 -08:00

loadstore_matrix.mlir

[MLIR][XeGPU] Allow create mem desc from 2d memref (#167767)

2025-11-18 21:31:17 -08:00

loadstore_nd.mlir

[MLIR][Conversion] XeGPU to XeVM: Add handler for 1D block ops (#165894)

2025-11-10 09:02:32 -08:00

loadstoreprefetch.mlir

[MLIR][XeVM] Update XeVM prefetch ops. (#166445)

2025-11-07 11:05:43 -08:00

materializecast.mlir

[MLIR][Conversion] Convert XeGPU to XeVM pass: Remove lowering support for tensor descriptor with offsets. (#157550)

2025-09-10 15:43:03 -07:00

prefetch_nd.mlir

[MLIR][XeVM] Update XeVM prefetch ops. (#166445)

2025-11-07 11:05:43 -08:00