497759e872
Fixes #107864 QEMU decided that when SVE is enabled it will only tell us about SVE registers in the XML, and not include Neon registers. On the grounds that the Neon V registers can be read from the bottom 128 bits of a SVE Z register (SVE's vector length is always >= 128 bits). To support this we create sub-registers just as we do for S and D registers of the V registers. Except this time we use part of the Z registers. This change also updates our fallback for registers with unknown types that are > 128 bit. This is detailed in https://github.com/llvm/llvm-project/issues/87471, though that covers more than this change fixes. We'll now treat any register of unknown type that is >= 128 bit as a vector of bytes. So that the user gets to see something even if the order might be wrong. And until lldb supports vector and union types for registers, this is also the only way we can get a value to apply the sub-reg to, to make the V registers.
203 lines
7.3 KiB
C++
203 lines
7.3 KiB
C++
//===-- AArch66.h ---------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "lldb/lldb-types.h"
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#include "ABIAArch64.h"
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#include "ABIMacOSX_arm64.h"
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#include "ABISysV_arm64.h"
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#include "Utility/ARM64_DWARF_Registers.h"
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#include "lldb/Core/PluginManager.h"
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#include "lldb/Target/Process.h"
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#include <bitset>
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#include <optional>
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using namespace lldb;
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LLDB_PLUGIN_DEFINE(ABIAArch64)
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void ABIAArch64::Initialize() {
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ABISysV_arm64::Initialize();
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ABIMacOSX_arm64::Initialize();
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}
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void ABIAArch64::Terminate() {
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ABISysV_arm64::Terminate();
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ABIMacOSX_arm64::Terminate();
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}
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lldb::addr_t ABIAArch64::FixCodeAddress(lldb::addr_t pc) {
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if (lldb::ProcessSP process_sp = GetProcessSP()) {
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// b55 is the highest bit outside TBI (if it's enabled), use
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// it to determine if the high bits are set to 0 or 1.
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const addr_t pac_sign_extension = 0x0080000000000000ULL;
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addr_t mask = process_sp->GetCodeAddressMask();
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// Test if the high memory mask has been overriden separately
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if (pc & pac_sign_extension &&
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process_sp->GetHighmemCodeAddressMask() != LLDB_INVALID_ADDRESS_MASK)
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mask = process_sp->GetHighmemCodeAddressMask();
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if (mask != LLDB_INVALID_ADDRESS_MASK)
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return FixAddress(pc, mask);
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}
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return pc;
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}
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lldb::addr_t ABIAArch64::FixDataAddress(lldb::addr_t pc) {
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if (lldb::ProcessSP process_sp = GetProcessSP()) {
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// b55 is the highest bit outside TBI (if it's enabled), use
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// it to determine if the high bits are set to 0 or 1.
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const addr_t pac_sign_extension = 0x0080000000000000ULL;
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addr_t mask = process_sp->GetDataAddressMask();
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// Test if the high memory mask has been overriden separately
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if (pc & pac_sign_extension &&
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process_sp->GetHighmemDataAddressMask() != LLDB_INVALID_ADDRESS_MASK)
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mask = process_sp->GetHighmemDataAddressMask();
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if (mask != LLDB_INVALID_ADDRESS_MASK)
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return FixAddress(pc, mask);
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}
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return pc;
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}
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std::pair<uint32_t, uint32_t>
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ABIAArch64::GetEHAndDWARFNums(llvm::StringRef name) {
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if (name == "pc")
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return {LLDB_INVALID_REGNUM, arm64_dwarf::pc};
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if (name == "cpsr")
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return {LLDB_INVALID_REGNUM, arm64_dwarf::cpsr};
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return MCBasedABI::GetEHAndDWARFNums(name);
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}
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std::string ABIAArch64::GetMCName(std::string reg) {
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MapRegisterName(reg, "v", "q");
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MapRegisterName(reg, "x29", "fp");
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MapRegisterName(reg, "x30", "lr");
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return reg;
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}
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uint32_t ABIAArch64::GetGenericNum(llvm::StringRef name) {
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return llvm::StringSwitch<uint32_t>(name)
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.Case("pc", LLDB_REGNUM_GENERIC_PC)
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.Cases("lr", "x30", LLDB_REGNUM_GENERIC_RA)
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.Cases("sp", "x31", LLDB_REGNUM_GENERIC_SP)
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.Cases("fp", "x29", LLDB_REGNUM_GENERIC_FP)
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.Case("cpsr", LLDB_REGNUM_GENERIC_FLAGS)
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.Case("x0", LLDB_REGNUM_GENERIC_ARG1)
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.Case("x1", LLDB_REGNUM_GENERIC_ARG2)
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.Case("x2", LLDB_REGNUM_GENERIC_ARG3)
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.Case("x3", LLDB_REGNUM_GENERIC_ARG4)
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.Case("x4", LLDB_REGNUM_GENERIC_ARG5)
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.Case("x5", LLDB_REGNUM_GENERIC_ARG6)
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.Case("x6", LLDB_REGNUM_GENERIC_ARG7)
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.Case("x7", LLDB_REGNUM_GENERIC_ARG8)
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.Default(LLDB_INVALID_REGNUM);
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}
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static void addPartialRegisters(
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std::vector<lldb_private::DynamicRegisterInfo::Register> ®s,
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llvm::ArrayRef<std::optional<uint32_t>> full_reg_indices,
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uint32_t full_reg_size, const char *partial_reg_format,
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uint32_t partial_reg_size, lldb::Encoding encoding, lldb::Format format) {
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for (auto it : llvm::enumerate(full_reg_indices)) {
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std::optional<uint32_t> full_reg_index = it.value();
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if (!full_reg_index || regs[*full_reg_index].byte_size != full_reg_size)
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return;
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lldb_private::DynamicRegisterInfo::Register partial_reg{
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lldb_private::ConstString(
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llvm::formatv(partial_reg_format, it.index()).str()),
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lldb_private::ConstString(),
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lldb_private::ConstString("supplementary registers"),
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partial_reg_size,
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LLDB_INVALID_INDEX32,
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encoding,
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format,
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LLDB_INVALID_REGNUM,
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LLDB_INVALID_REGNUM,
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LLDB_INVALID_REGNUM,
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LLDB_INVALID_REGNUM,
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{*full_reg_index},
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{}};
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addSupplementaryRegister(regs, partial_reg);
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}
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}
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void ABIAArch64::AugmentRegisterInfo(
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std::vector<lldb_private::DynamicRegisterInfo::Register> ®s) {
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lldb_private::MCBasedABI::AugmentRegisterInfo(regs);
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lldb_private::ConstString sp_string{"sp"};
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std::array<std::optional<uint32_t>, 32> x_regs;
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std::array<std::optional<uint32_t>, 32> v_regs;
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std::array<std::optional<uint32_t>, 32> z_regs;
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std::optional<uint32_t> z_byte_size;
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for (auto it : llvm::enumerate(regs)) {
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lldb_private::DynamicRegisterInfo::Register &info = it.value();
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// GDB sends x31 as "sp". Add the "x31" alt_name for convenience.
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if (info.name == sp_string && !info.alt_name)
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info.alt_name.SetCString("x31");
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unsigned int reg_num;
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auto get_reg = [&info, ®_num](const char *prefix) {
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llvm::StringRef reg_name = info.name.GetStringRef();
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llvm::StringRef alt_name = info.alt_name.GetStringRef();
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return (reg_name.consume_front(prefix) &&
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llvm::to_integer(reg_name, reg_num, 10) && reg_num < 32) ||
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(alt_name.consume_front(prefix) &&
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llvm::to_integer(alt_name, reg_num, 10) && reg_num < 32);
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};
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if (get_reg("x"))
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x_regs[reg_num] = it.index();
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else if (get_reg("v"))
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v_regs[reg_num] = it.index();
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else if (get_reg("z")) {
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z_regs[reg_num] = it.index();
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if (!z_byte_size)
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z_byte_size = info.byte_size;
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}
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// if we have at least one subregister, abort
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else if (get_reg("w") || get_reg("s") || get_reg("d"))
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return;
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}
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// Create aliases for partial registers.
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// Wn for Xn.
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addPartialRegisters(regs, x_regs, 8, "w{0}", 4, lldb::eEncodingUint,
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lldb::eFormatHex);
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auto bool_predicate = [](const auto ®_num) { return bool(reg_num); };
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bool saw_v_regs = std::any_of(v_regs.begin(), v_regs.end(), bool_predicate);
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bool saw_z_regs = std::any_of(z_regs.begin(), z_regs.end(), bool_predicate);
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// Sn/Dn for Vn.
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if (saw_v_regs) {
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addPartialRegisters(regs, v_regs, 16, "s{0}", 4, lldb::eEncodingIEEE754,
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lldb::eFormatFloat);
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addPartialRegisters(regs, v_regs, 16, "d{0}", 8, lldb::eEncodingIEEE754,
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lldb::eFormatFloat);
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} else if (saw_z_regs && z_byte_size) {
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// When SVE is enabled, some debug stubs will not describe the Neon V
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// registers because they can be read from the bottom 128 bits of the SVE
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// registers.
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// The size used here is the one sent by the debug server. This only needs
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// to be correct right now. Later we will rely on the value of vg instead.
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addPartialRegisters(regs, z_regs, *z_byte_size, "v{0}", 16,
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lldb::eEncodingVector, lldb::eFormatVectorOfUInt8);
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addPartialRegisters(regs, z_regs, *z_byte_size, "s{0}", 4,
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lldb::eEncodingIEEE754, lldb::eFormatFloat);
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addPartialRegisters(regs, z_regs, *z_byte_size, "d{0}", 8,
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lldb::eEncodingIEEE754, lldb::eFormatFloat);
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}
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}
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