Michael Maitland 6bac41496e

[RISCV][GISEL] Legalize G_INSERT_SUBVECTOR (#108859) ...

This code is heavily based on the SelectionDAG lowerINSERT_SUBVECTOR
code.

2024-10-21 08:49:13 -04:00

..

RISCVCallLowering.cpp

[RISCV] Reduce the interface to RISCVCCAssignFn. NFC (#107503)

2024-09-06 09:28:33 -07:00

RISCVCallLowering.h

[RISCV][GISel] Implement canLowerReturn. (#105465)

2024-08-22 08:12:51 -07:00

RISCVInstructionSelector.cpp

[RISCV][GISEL][NFC] Add break statement to reduce diff on future changes of preISelLower

2024-10-07 07:23:52 -07:00

RISCVLegalizerInfo.cpp

[RISCV][GISEL] Legalize G_INSERT_SUBVECTOR (#108859)

2024-10-21 08:49:13 -04:00

RISCVLegalizerInfo.h

[RISCV][GISEL] Legalize G_INSERT_SUBVECTOR (#108859)

2024-10-21 08:49:13 -04:00

RISCVO0PreLegalizerCombiner.cpp

[RISCV][GISel] Add a post legalizer combiner and enable a couple comb… (#67053)

2023-09-22 10:13:56 -07:00

RISCVPostLegalizerCombiner.cpp

[CodeGen][NewPM] Split MachineDominatorTree into a concrete analysis result (#94571)

2024-06-11 21:27:14 +08:00

RISCVPreLegalizerCombiner.cpp

[CodeGen][NewPM] Split MachineDominatorTree into a concrete analysis result (#94571)

2024-06-11 21:27:14 +08:00

RISCVRegisterBankInfo.cpp

[RISCV][GISEL] regbankselect for G_SPLAT_VECTOR (#110744)

2024-10-01 21:50:21 -04:00

RISCVRegisterBankInfo.h

[GISel][TableGen] Generate getRegBankFromRegClass (#99896)

2024-07-25 09:41:55 -04:00

RISCVRegisterBanks.td

[RISCV][GISEL] Add vector RegisterBanks and vector support in getRegBankFromRegClass

2023-11-15 15:08:29 -08:00