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llvm-project/llvm/test/CodeGen/Thumb2/LowOverheadLoops
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Florian Hahn 2f7ccaf4a8
[SCEV] Add predicate in SolveLinEq to ensure B is a multiple of A. (#108777) 
This can help in cases where pointer alignment info is missing, e.g.
https://github.com/llvm/llvm-project/pull/108210

The predicate is formed for the complex expression that's passed to
SolveLinEquationWithOverflow and the checks could probably be pushed
closer to the root nodes, which in some cases may be cheaper to check.


PR: https://github.com/llvm/llvm-project/pull/108777
2024-09-28 14:19:57 +01:00
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add_reduce.mir
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arm_cmplx_dot_prod_f32.ll
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begin-vpt-without-inst.mir
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biquad-cascade-default.mir
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biquad-cascade-optsize-strd-lr.mir
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biquad-cascade-optsize.mir
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branch-targets.ll
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clear-maskedinsts.ll
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cmplx_cong.mir
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cond-mov.mir
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cond-vector-reduce-mve-codegen.ll
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constbound.ll
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count_dominates_start.mir
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ctlz-non-zeros.mir
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disjoint-vcmp.mir
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dont-ignore-vctp.mir
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dont-remove-loop-update.mir
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emptyblock.mir
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end-positive-offset.mir
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exitcount.ll
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extending-loads.ll
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extract-element.mir
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fast-fp-loops.ll
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incorrect-sub-8.mir
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incorrect-sub-16.mir
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incorrect-sub-32.mir
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inlineasm.ll
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inloop-vpnot-1.mir
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inloop-vpnot-2.mir
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inloop-vpnot-3.mir
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inloop-vpsel-1.mir
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inloop-vpsel-2.mir
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invariant-qreg.mir
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it-block-chain-store.mir
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it-block-chain.mir
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it-block-itercount.mir
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it-block-mov.mir
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it-block-random.mir
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iv-two-vcmp-reordered.mir
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iv-two-vcmp.mir
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iv-vcmp.mir
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livereg-no-loop-def.mir
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loop-dec-copy-chain.mir
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loop-dec-copy-prev-iteration.mir
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loop-dec-liveout.mir
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loop-guards.ll
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lsr-profitable-chain.ll
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lstp-insertion-position.mir
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massive.mir
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matrix-debug.mir
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matrix.mir
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memcall.ll
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minloop.ll
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mov-after-dls.mir
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mov-after-dlstp.mir
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mov-lr-terminator.mir
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mov-operand.ll
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move-def-before-start.mir
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move-start-after-def.mir
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multi-block-cond-iter-count.mir
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multi-cond-iter-count.mir
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multiblock-massive.mir
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multiple-do-loops.mir
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mve-float-loops.ll
[SCEV] Add predicate in SolveLinEq to ensure B is a multiple of A. (#108777)
2024-09-28 14:19:57 +01:00
mve-reduct-livein-arg.mir
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mve-tail-data-types.ll
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nested.ll
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no-dec-cbnz.mir
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no-dec-le-simple.ll
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no-dec-reorder.mir
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no-dec.mir
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no-vpsel-liveout.mir
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non-masked-load.mir
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non-masked-store.mir
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out-of-range-cbz.mir
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predicated-invariant.mir
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predicated-liveout-unknown-lanes.ll
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predicated-liveout.mir
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reductions-vpt-liveout.mir
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reductions.ll
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remat-vctp.ll
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remove-elem-moves.mir
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revert-after-call.mir
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revert-after-read.mir
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revert-after-write.mir
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revert-non-header.mir
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revert-non-loop.mir
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revert-while.mir
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revertcallearly.mir
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safe-def-no-mov.mir
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safe-retaining.mir
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sibling-loops.ll
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size-limit.mir
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skip-debug.mir
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skip-vpt-debug.mir
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spillingmove.ll
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spillingmove.mir
[CodeGen] Remove target SubRegLiveness flags (#95437)
2024-06-14 08:51:56 +01:00
subreg-liveness.mir
[CodeGen] Remove target SubRegLiveness flags (#95437)
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switch.mir
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tail-pred-basic.ll
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tail-pred-const.ll
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tail-pred-disabled-in-loloops.ll
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tail-pred-intrinsic-add-sat.ll
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tail-pred-intrinsic-fabs.ll
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tail-pred-intrinsic-round.ll
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tail-pred-intrinsic-sub-sat.ll
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tail-pred-narrow.ll
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tail-pred-pattern-fail.ll
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tail-pred-reduce.ll
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tail-pred-widen.ll
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tp-multiple-vpst.ll
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unpredicated-max.mir
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unpredload.ll
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unrolled-and-vector.mir
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unsafe-cpsr-loop-def.mir
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unsafe-cpsr-loop-use.mir
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unsafe-retaining.mir
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unsafe-use-after.mir
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vaddv.mir
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varying-outer-2d-reduction.ll
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vcmp-vpst-combination-across-blocks.mir
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vcmp-vpst-combination.ll
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vctp16-reduce.mir
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vctp-add-operand-liveout.mir
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vctp-in-vpt-2.mir
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vctp-in-vpt.mir
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vctp-subi3.mir
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vctp-subri12.mir
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vctp-subri.mir
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vector_spill_in_loop.mir
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vector-arith-codegen.ll
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vector-reduce-mve-tail.ll
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vector-unroll.ll
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vmaxmin_vpred_r.mir
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vmldava_in_vpt.mir
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vpt-block-debug.mir
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vpt-blocks.mir
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while-loops.ll
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while-negative-offset.mir
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while.mir
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wls-revert-placement.mir
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wls-search-killed.mir
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wls-search-pred.mir
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wlstp.mir
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wrong-liveout-lsr-shift.mir
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wrong-vctp-opcode-liveout.mir
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wrong-vctp-operand-liveout.mir
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