Observer007 2b23e6c8d6

[mlir][nvgpu] Add nvgpu.rcp OP (#100965) ...

This PR introduces a new OP for reciprocal calculation for `vector`
types using `nvvm.rcp` OPs. Currently, it supports only f32 types

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Co-authored-by: jingzec <jingzec@nvidia.com>

2024-07-30 09:20:49 +02:00

..

canonicalization.mlir

[mlir][nvgpu] Mark TMA descriptor as MemWriteAt in tma.async.store (#79427)

2024-01-30 19:36:59 +01:00

invalid.mlir

[mlir][nvgpu] Add nvgpu.rcp OP (#100965)

2024-07-30 09:20:49 +02:00

mma-sync-f32-to-tf32.mlir

[mlir][NFC] Remove trailing whitespaces from *.td and *.mlir files.

2022-11-28 15:26:30 -08:00

mma-sync-f32-to-tf32x3.mlir

[mlir][NFC] Remove trailing whitespaces from *.td and *.mlir files.

2022-11-28 15:26:30 -08:00

optimize-shared-memory.mlir

[mlir][nvgpu] Verify invalid copy size (nfc)

2023-07-17 17:09:33 +02:00

roundtrip.mlir

[mlir][NVGPU] Add support for structured sparsity MMA variants

2022-11-07 09:43:03 -07:00

tmaload-transform.mlir

[mlir][nvgpu] Make phaseParity of mbarrier.try_wait i1 (#81460)

2024-02-13 09:50:34 +01:00

transform-create-async-groups.mlir

[mlir][Transforms] GreedyPatternRewriteDriver: Do not CSE constants during iterations (#75897)

2024-01-05 09:22:18 +01:00

transform-matmul-to-nvvm.mlir

[mlir] use transform-interpreter in test passes (#70040)

2023-10-24 16:12:34 +02:00

transform-pipeline-shared.mlir

[MLIR][SCF] Add support for pipelining dynamic loops (#74350)

2023-12-10 22:32:11 -08:00