fe55c34d19
To run integration tests using qemu-aarch64 on x64 host, below flags are
added to the cmake command when building mlir/llvm:
-DMLIR_INCLUDE_INTEGRATION_TESTS=ON \
-DMLIR_RUN_ARM_SVE_TESTS=ON \
-DMLIR_RUN_ARM_SME_TESTS=ON \
-DARM_EMULATOR_EXECUTABLE="<...>/qemu-aarch64" \
-DARM_EMULATOR_OPTIONS="-L /usr/aarch64-linux-gnu" \
-DARM_EMULATOR_MLIR_CPU_RUNNER_EXECUTABLE="<llvm_arm64_build_top>/bin/mlir-cpu-runner-arm64"
\
-DARM_EMULATOR_LLI_EXECUTABLE="<llvm_arm64_build_top>/bin/lli" \
-DARM_EMULATOR_UTILS_LIB_DIR="<llvm_arm64_build_top>/lib"
The last three above are prebuilt on, or cross-built for, an aarch64
host.
This patch introduced substittutions of "%native_mlir_runner_utils" etc. and use
them in SVE/SME integration tests. When configured to run using qemu-aarch64,
mlir runtime util libs will be loaded from ARM_EMULATOR_UTILS_LIB_DIR, if set.
Some tests marked with 'UNSUPPORTED: target=aarch64{{.*}}' are still run
when configured with ARM_EMULATOR_EXECUTABLE and the default target is
not aarch64.
A lit config feature 'mlir_arm_emulator' is added in
mlir/test/lit.site.cfg.py.in and to UNSUPPORTED list of such tests.
75 lines
2.3 KiB
MLIR
75 lines
2.3 KiB
MLIR
// DEFINE: %{entry_point} = entry
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// DEFINE: %{compile} = mlir-opt %s -test-lower-to-arm-sme -test-lower-to-llvm
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// DEFINE: %{run} = %mcr_aarch64_cmd \
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// DEFINE: -march=aarch64 -mattr=+sve,+sme \
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// DEFINE: -e %{entry_point} -entry-point-result=void \
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// DEFINE: -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils,%native_arm_sme_abi_shlib
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// RUN: %{compile} | %{run} | FileCheck %s
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func.func @entry() {
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%c0 = arith.constant 0 : index
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%c1 = arith.constant 1 : index
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%c1_i32 = arith.constant 1 : i32
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// Calculate the size of a 32-bit tile, e.g. ZA{n}.s.
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%svl_s = arm_sme.streaming_vl <word>
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%za_s_size = arith.muli %svl_s, %svl_s : index
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// Allocate memory.
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%mem1 = memref.alloca(%za_s_size) : memref<?xi32>
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// Fill each "row" of "mem1" with row number.
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//
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// For example, assuming an SVL of 128-bits:
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//
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// 0, 0, 0, 0
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// 1, 1, 1, 1
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// 2, 2, 2, 2
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// 3, 3, 3, 3
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//
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%init_0 = arith.constant 0 : i32
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scf.for %i = %c0 to %za_s_size step %svl_s iter_args(%val = %init_0) -> (i32) {
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%splat_val = vector.broadcast %val : i32 to vector<[4]xi32>
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vector.store %splat_val, %mem1[%i] : memref<?xi32>, vector<[4]xi32>
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%val_next = arith.addi %val, %c1_i32 : i32
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scf.yield %val_next : i32
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}
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// Load tile from "mem1" vertically.
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%0 = arm_sme.tile_load %mem1[%c0, %c0] layout<vertical> : memref<?xi32>, vector<[4]x[4]xi32>
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// 1. ORIGINAL HORIZONTAL LAYOUT
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// Dump "mem1". The smallest SVL is 128-bits so the tile will be at least
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// 4x4xi32.
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//
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// CHECK: TILE BEGIN
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// CHECK-NEXT: ( 0, 0, 0, 0
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// CHECK-NEXT: ( 1, 1, 1, 1
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// CHECK-NEXT: ( 2, 2, 2, 2
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// CHECK-NEXT: ( 3, 3, 3, 3
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// CHECK: TILE END
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vector.print str "TILE BEGIN\n"
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scf.for %i = %c0 to %za_s_size step %svl_s {
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%tileslice = vector.load %mem1[%i] : memref<?xi32>, vector<[4]xi32>
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vector.print %tileslice : vector<[4]xi32>
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}
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vector.print str "TILE END\n"
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// 2. VERTICAL LAYOUT
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// Dump "mem2". The smallest SVL is 128-bits so the tile will be at least
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// 4x4xi32.
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//
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// CHECK: TILE BEGIN
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// CHECK-NEXT: ( 0, 1, 2, 3
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// CHECK-NEXT: ( 0, 1, 2, 3
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// CHECK-NEXT: ( 0, 1, 2, 3
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// CHECK-NEXT: ( 0, 1, 2, 3
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// CHECK: TILE END
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vector.print str "TILE BEGIN\n"
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vector.print %0 : vector<[4]x[4]xi32>
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vector.print str "TILE END\n"
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return
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}
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