shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity
llvm-project/llvm/test/CodeGen
History
LU-JOHN 896d900c9b
[AMDGPU] Create hi-half of 64-bit ashr with mov of -1 (#146569) 
When performing a 64-bit sra of a negative value with a shift range from
[32-63], create the hi-half with a move of -1.

Alive verification: https://alive2.llvm.org/ce/z/kXd7Ac

Also, preserve exact flag. Alive verification:
https://alive2.llvm.org/ce/z/L86tXf.

---------

Signed-off-by: John Lu <John.Lu@amd.com>
2025-07-09 12:02:51 -04:00
..
AArch64
[AArch64][PAC] Protect the entire function if pac-ret+leaf is requested (#140895)
2025-07-09 18:40:45 +03:00
AMDGPU
[AMDGPU] Create hi-half of 64-bit ashr with mov of -1 (#146569)
2025-07-09 12:02:51 -04:00
ARC
…
ARM
CodeGen: Remove redundant REQUIRES registered-target from backend tests (#147475)
2025-07-09 09:25:53 +09:00
AVR
DAG: Fall back to separate sin and cos when softening sincos (#147468)
2025-07-09 01:52:46 +09:00
BPF
[BPF] Handle nested wrapper structs in BPF map definition traversal (#144097)
2025-06-20 10:17:36 -07:00
CSKY
…
DirectX
[DirectX] Lower llvm.lifetime.* intrinsics to stores when DXIL version is lower than 1.6 (#147432)
2025-07-08 14:45:14 -07:00
Generic
[RemoveDIs] Fix rotten --implicit-check-not lines (#144711)
2025-06-24 12:32:50 +01:00
Hexagon
[Hexagon] Handle Call Operand vxi1 in Hexagon without HVX Enabled (#136546)
2025-07-08 09:43:15 -07:00
Inputs
…
Lanai
…
LoongArch
LoongArch: Add test for sincos intrinsic (#147471)
2025-07-09 02:01:54 +09:00
M68k
…
Mips
[MIPS] ins.ll - regenerate test checks
2025-07-07 18:31:13 +01:00
MIR
[NVPTX] Fixup v2i8 parameter and return lowering (#145585)
2025-06-27 09:26:10 -07:00
MLRegAlloc
Revert "[mlgo][regalloc] Fix after PR #131837" (#146897)
2025-07-03 07:11:59 -07:00
MSP430
DAG: Fix asserting in error case for powi softening (#147237)
2025-07-07 18:13:11 +09:00
NVPTX
AtomicExpand: Stop using report_fatal_error (#147300)
2025-07-09 15:28:10 +09:00
PowerPC
[XRay] xray_fn_idx: fix alignment directive
2025-07-08 21:52:53 -07:00
RISCV
[RISCV] Convert the XAndesVSIntLoad intrinsic tests to opaque pointers. NFC
2025-07-09 23:10:59 +08:00
SPARC
SPARC: Add sincos intrinsic test (#147464)
2025-07-09 09:21:46 +09:00
SPIRV
[SPIRV] Add more id and range builtIns (#143909)
2025-07-09 13:52:06 +01:00
SystemZ
[XRay] xray_fn_idx: fix alignment directive
2025-07-08 21:52:53 -07:00
Thumb
…
Thumb2
[PHIElimination] Revert #131837 #146320 #146337 (#146850)
2025-07-03 07:48:08 -04:00
VE
[PHIElimination] Revert #131837 #146320 #146337 (#146850)
2025-07-03 07:48:08 -04:00
WebAssembly
CodeGen: Remove redundant REQUIRES registered-target from backend tests (#147475)
2025-07-09 09:25:53 +09:00
WinCFGuard
…
WinEH
…
X86
[X86] combineBasicSADPattern - pattern match various vXi8 ABDU patterns (#147570)
2025-07-09 08:08:22 +01:00
XCore
…
Xtensa
[Xtensa] Implement THREADPTR and DFPAccel Xtensa Options. (#145543)
2025-07-02 17:47:07 +03:00