2b4a462e95
The new format matches the official ISA spec and ensures the disassembler prints 'export mrt0, v0, off, off, off' instead of 'export mrt0 v0, off, off, off'. No functional encoding changes; printing/AsmString only.
59 lines
2.3 KiB
LLVM
59 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck %s -check-prefixes=GFX10
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declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i1 immarg)
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declare i32 @llvm.amdgcn.raw.ptr.buffer.atomic.and.i32(i32, ptr addrspace(8), i32, i32, i32 immarg)
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declare float @llvm.amdgcn.strict.wqm.f32(float)
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define amdgpu_ps void @main(i32 %arg) {
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; GFX10-LABEL: main:
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; GFX10: ; %bb.0: ; %bb
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; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
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; GFX10-NEXT: v_mov_b32_e32 v0, 0
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; GFX10-NEXT: s_mov_b32 s1, exec_lo
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; GFX10-NEXT: s_mov_b32 s4, 0
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; GFX10-NEXT: s_mov_b32 s2, 0
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; GFX10-NEXT: s_branch .LBB0_2
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; GFX10-NEXT: .LBB0_1: ; in Loop: Header=BB0_2 Depth=1
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; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
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; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s3
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; GFX10-NEXT: s_and_b32 s0, exec_lo, vcc_lo
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; GFX10-NEXT: s_or_b32 s2, s0, s2
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; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s2
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; GFX10-NEXT: s_cbranch_execz .LBB0_5
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; GFX10-NEXT: .LBB0_2: ; %bb4
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; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
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; GFX10-NEXT: s_and_saveexec_b32 s3, s1
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; GFX10-NEXT: s_cbranch_execz .LBB0_1
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; GFX10-NEXT: ; %bb.3: ; in Loop: Header=BB0_2 Depth=1
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; GFX10-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
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; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v1
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; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s0
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; GFX10-NEXT: s_cbranch_execz .LBB0_1
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; GFX10-NEXT: ; %bb.4: ; in Loop: Header=BB0_2 Depth=1
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; GFX10-NEXT: s_mov_b32 s5, s4
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; GFX10-NEXT: s_mov_b32 s6, s4
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; GFX10-NEXT: s_mov_b32 s7, s4
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; GFX10-NEXT: buffer_atomic_and v0, off, s[4:7], 0
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; GFX10-NEXT: s_branch .LBB0_1
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; GFX10-NEXT: .LBB0_5: ; %bb8
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; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s2
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; GFX10-NEXT: s_mov_b32 s0, 0
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; GFX10-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-NEXT: v_mov_b32_e32 v0, s0
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; GFX10-NEXT: exp mrt0, off, off, off, off
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; GFX10-NEXT: s_endpgm
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bb:
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br label %bb4
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bb4:
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%i5 = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.and.i32(i32 0, ptr addrspace(8) null, i32 0, i32 0, i32 0)
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%i7 = icmp eq i32 %arg, 1
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br i1 %i7, label %bb8, label %bb4
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bb8:
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%i9 = call float @llvm.amdgcn.strict.wqm.f32(float 0.0)
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call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float %i9, float 0.0, float 0.0, float 0.0, i1 false, i1 false)
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ret void
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}
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