40270e8ef2
Cover all the missing cases and add very detailed tests for each rule. In summary: - Flat and Scratch, addrspace(0) and addrspace(5), loads are always divergent. - Global and Constant, addrspace(1) and addrspace(4), have real uniform loads, s_load, but require additional checks for align and flags in mmo. For not natural align or not uniform mmo do uniform-in-vgpr lowering. - Private, addrspace(3), only has instructions for divergent load, for uniform do uniform-in-vgpr lowering. - Store rules are simplified using Ptr32 and Ptr64. All operands need to be vgpr. Some tests have code size regression since they use more sgpr instructions, marked with FixMe comment to get back to later.
58 lines
2.1 KiB
LLVM
58 lines
2.1 KiB
LLVM
; RUN: llc -global-isel=0 -mtriple=amdgcn--amdhsa < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn--amdhsa < %s | FileCheck -check-prefix=GCN %s
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declare i64 @llvm.amdgcn.dispatch.id() #1
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; GCN-LABEL: {{^}}dispatch_id:
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; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s10
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; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], s11
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; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[LO]]:[[HI]]]
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; GCN: .amdhsa_user_sgpr_dispatch_id 1
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define amdgpu_kernel void @dispatch_id(ptr addrspace(1) %out) #0 {
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%tmp0 = call i64 @llvm.amdgcn.dispatch.id()
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store i64 %tmp0, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}dispatch_id_opt0:
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; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s8
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; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], s9
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; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[LO]]:[[HI]]]
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; GCN: .amdhsa_user_sgpr_dispatch_id 1
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define amdgpu_kernel void @dispatch_id_opt0(ptr addrspace(1) %out) #2 {
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%tmp0 = call i64 @llvm.amdgcn.dispatch.id()
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store i64 %tmp0, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}dispatch_id_opt1:
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; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s6
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; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], s7
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; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[LO]]:[[HI]]]
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; GCN: .amdhsa_user_sgpr_dispatch_id 1
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define amdgpu_kernel void @dispatch_id_opt1(ptr addrspace(1) %out) #3 {
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%tmp0 = call i64 @llvm.amdgcn.dispatch.id()
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store i64 %tmp0, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}dispatch_id_opt2:
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; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s4
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; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], s5
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; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[LO]]:[[HI]]]
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; GCN: .amdhsa_user_sgpr_dispatch_id 1
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define amdgpu_kernel void @dispatch_id_opt2() #4 {
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%tmp0 = call i64 @llvm.amdgcn.dispatch.id()
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store i64 %tmp0, ptr addrspace(1) null
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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attributes #2 = { "amdgpu-no-dispatch-ptr" }
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attributes #3 = { "amdgpu-no-dispatch-ptr" "amdgpu-no-queue-ptr" }
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attributes #4 = { "amdgpu-no-dispatch-ptr" "amdgpu-no-queue-ptr" "amdgpu-no-implicitarg-ptr" }
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!llvm.module.flags = !{!0}
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!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}
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