e95f6fa123
Introduce a target hook to incrementally flip the behavior of targets with test changes, and start by implementing it for AMDGPU. This appears to be forgotten switch flip from 2015. This seems to do a nicer job with subregister copies. Most of the test changes are improvements or neutral, not that many are light regressions. The worst AMDGPU regressions are for true16 in the atomic tests, but I think that's due to existing true16 issues.
92 lines
3.2 KiB
LLVM
92 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=verde < %s | FileCheck -enable-var-scope -check-prefixes=GCN %s
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define amdgpu_kernel void @zext_i16_to_i32_uniform(ptr addrspace(1) %out, i16 %a, i32 %b) {
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; GCN-LABEL: zext_i16_to_i32_uniform:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_mov_b64 s[4:5], s[2:3]
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; GCN-NEXT: s_and_b32 s4, s4, 0xffff
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; GCN-NEXT: s_add_i32 s4, s5, s4
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_mov_b32 s2, -1
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; GCN-NEXT: v_mov_b32_e32 v0, s4
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; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GCN-NEXT: s_endpgm
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%zext = zext i16 %a to i32
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%res = add i32 %b, %zext
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store i32 %res, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @zext_i16_to_i64_uniform(ptr addrspace(1) %out, i16 %a, i64 %b) {
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; GCN-LABEL: zext_i16_to_i64_uniform:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dword s8, s[4:5], 0xb
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; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0xd
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_mov_b32 s2, -1
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_and_b32 s4, s8, 0xffff
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; GCN-NEXT: s_add_u32 s4, s6, s4
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; GCN-NEXT: s_addc_u32 s5, s7, 0
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; GCN-NEXT: v_mov_b32_e32 v0, s4
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; GCN-NEXT: v_mov_b32_e32 v1, s5
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; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; GCN-NEXT: s_endpgm
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%zext = zext i16 %a to i64
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%res = add i64 %b, %zext
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store i64 %res, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @zext_i16_to_i32_divergent(ptr addrspace(1) %out, i16 %a, i32 %b) {
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; GCN-LABEL: zext_i16_to_i32_divergent:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dword s6, s[4:5], 0xb
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_mov_b32 s2, -1
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_add_i32_e32 v0, vcc, s6, v0
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; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
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; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GCN-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.truncated = trunc i32 %tid to i16
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%divergent.a = add i16 %a, %tid.truncated
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%zext = zext i16 %divergent.a to i32
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store i32 %zext, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @zext_i16_to_i64_divergent(ptr addrspace(1) %out, i16 %a, i64 %b) {
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; GCN-LABEL: zext_i16_to_i64_divergent:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dword s6, s[4:5], 0xb
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_mov_b32 s2, -1
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_add_i32_e32 v0, vcc, s6, v0
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; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
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; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; GCN-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.truncated = trunc i32 %tid to i16
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%divergent.a = add i16 %a, %tid.truncated
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%zext = zext i16 %divergent.a to i64
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store i64 %zext, ptr addrspace(1) %out
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone speculatable }
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