0d4a35d560
These are long overdue for removal. These were originally a hack to support loading half values before there was any / decent support for the half type through the backend. There's no reason to continue supporting these, they're equivalent to fpext/fptrunc with a bitcast. SelectionDAG stopped translating these directly, and used the bitcast + fp cast since f7a02c17628e825, so there's been no reason to use these since 2014.
444 lines
12 KiB
LLVM
444 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc %s -o - -mtriple=avr | FileCheck %s
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; Tests for various operations on half precison float. Much of the test is
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; copied from test/CodeGen/X86/half.ll.
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define void @store(half %x, ptr %p) nounwind {
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; CHECK-LABEL: store:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: mov r30, r22
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; CHECK-NEXT: mov r31, r23
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; CHECK-NEXT: std Z+1, r25
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; CHECK-NEXT: st Z, r24
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; CHECK-NEXT: ret
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store half %x, ptr %p
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ret void
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}
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define half @return(ptr %p) nounwind {
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; CHECK-LABEL: return:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: mov r30, r24
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; CHECK-NEXT: mov r31, r25
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; CHECK-NEXT: ld r24, Z
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; CHECK-NEXT: ldd r25, Z+1
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; CHECK-NEXT: ret
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%r = load half, ptr %p
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ret half %r
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}
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define void @test_load_store(ptr %in, ptr %out) nounwind {
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; CHECK-LABEL: test_load_store:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: mov r30, r24
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; CHECK-NEXT: mov r31, r25
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; CHECK-NEXT: ld r24, Z
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; CHECK-NEXT: ldd r25, Z+1
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; CHECK-NEXT: mov r30, r22
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; CHECK-NEXT: mov r31, r23
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; CHECK-NEXT: std Z+1, r25
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; CHECK-NEXT: st Z, r24
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; CHECK-NEXT: ret
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%val = load half, ptr %in
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store half %val, ptr %out
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ret void
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}
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define i16 @test_bitcast_from_half(ptr %addr) nounwind {
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; CHECK-LABEL: test_bitcast_from_half:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: mov r30, r24
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; CHECK-NEXT: mov r31, r25
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; CHECK-NEXT: ld r24, Z
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; CHECK-NEXT: ldd r25, Z+1
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; CHECK-NEXT: ret
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%val = load half, ptr %addr
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%val_int = bitcast half %val to i16
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ret i16 %val_int
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}
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define void @test_bitcast_to_half(ptr %addr, i16 %in) nounwind {
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; CHECK-LABEL: test_bitcast_to_half:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: mov r30, r24
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; CHECK-NEXT: mov r31, r25
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; CHECK-NEXT: std Z+1, r23
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; CHECK-NEXT: st Z, r22
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; CHECK-NEXT: ret
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%val_fp = bitcast i16 %in to half
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store half %val_fp, ptr %addr
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ret void
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}
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define half @from_bits(i16 %x) nounwind {
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; CHECK-LABEL: from_bits:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: ret
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%res = bitcast i16 %x to half
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ret half %res
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}
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define i16 @to_bits(half %x) nounwind {
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; CHECK-LABEL: to_bits:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: ret
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%res = bitcast half %x to i16
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ret i16 %res
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}
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define float @test_extend32(ptr %addr) nounwind {
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; CHECK-LABEL: test_extend32:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: mov r30, r24
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; CHECK-NEXT: mov r31, r25
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; CHECK-NEXT: ld r24, Z
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; CHECK-NEXT: ldd r25, Z+1
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; CHECK-NEXT: rcall __extendhfsf2
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; CHECK-NEXT: ret
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%val16 = load half, ptr %addr
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%val32 = fpext half %val16 to float
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ret float %val32
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}
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define double @test_extend64(ptr %addr) nounwind {
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; CHECK-LABEL: test_extend64:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: mov r30, r24
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; CHECK-NEXT: mov r31, r25
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; CHECK-NEXT: ld r24, Z
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; CHECK-NEXT: ldd r25, Z+1
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; CHECK-NEXT: rcall __extendhfsf2
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; CHECK-NEXT: rcall __extendsfdf2
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; CHECK-NEXT: ret
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%val16 = load half, ptr %addr
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%val32 = fpext half %val16 to double
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ret double %val32
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}
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define void @test_trunc32(float %in, ptr %addr) nounwind {
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; CHECK-LABEL: test_trunc32:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: push r16
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; CHECK-NEXT: push r17
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; CHECK-NEXT: mov r16, r20
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; CHECK-NEXT: mov r17, r21
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; CHECK-NEXT: rcall __truncsfhf2
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; CHECK-NEXT: mov r30, r16
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; CHECK-NEXT: mov r31, r17
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; CHECK-NEXT: std Z+1, r25
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; CHECK-NEXT: st Z, r24
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; CHECK-NEXT: pop r17
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; CHECK-NEXT: pop r16
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; CHECK-NEXT: ret
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%val16 = fptrunc float %in to half
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store half %val16, ptr %addr
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ret void
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}
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define void @test_trunc64(double %in, ptr %addr) nounwind {
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; CHECK-LABEL: test_trunc64:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: rcall __truncdfhf2
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; CHECK-NEXT: mov r30, r16
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; CHECK-NEXT: mov r31, r17
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; CHECK-NEXT: std Z+1, r25
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; CHECK-NEXT: st Z, r24
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; CHECK-NEXT: ret
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%val16 = fptrunc double %in to half
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store half %val16, ptr %addr
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ret void
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}
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define i64 @test_fptosi_i64(ptr %p) nounwind {
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; CHECK-LABEL: test_fptosi_i64:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: mov r30, r24
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; CHECK-NEXT: mov r31, r25
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; CHECK-NEXT: ld r24, Z
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; CHECK-NEXT: ldd r25, Z+1
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; CHECK-NEXT: rcall __extendhfsf2
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; CHECK-NEXT: rcall __fixsfdi
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; CHECK-NEXT: ret
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%a = load half, ptr %p, align 2
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%r = fptosi half %a to i64
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ret i64 %r
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}
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define void @test_sitofp_i64(i64 %a, ptr %p) nounwind {
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; CHECK-LABEL: test_sitofp_i64:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: rcall __floatdisf
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; CHECK-NEXT: rcall __truncsfhf2
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; CHECK-NEXT: mov r30, r16
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; CHECK-NEXT: mov r31, r17
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; CHECK-NEXT: std Z+1, r25
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; CHECK-NEXT: st Z, r24
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; CHECK-NEXT: ret
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%r = sitofp i64 %a to half
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store half %r, ptr %p
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ret void
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}
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define i64 @test_fptoui_i64(ptr %p) nounwind {
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; CHECK-LABEL: test_fptoui_i64:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: mov r30, r24
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; CHECK-NEXT: mov r31, r25
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; CHECK-NEXT: ld r24, Z
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; CHECK-NEXT: ldd r25, Z+1
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; CHECK-NEXT: rcall __extendhfsf2
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; CHECK-NEXT: rcall __fixunssfdi
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; CHECK-NEXT: ret
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%a = load half, ptr %p, align 2
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%r = fptoui half %a to i64
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ret i64 %r
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}
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define void @test_uitofp_i64(i64 %a, ptr %p) nounwind {
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; CHECK-LABEL: test_uitofp_i64:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: rcall __floatundisf
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; CHECK-NEXT: rcall __truncsfhf2
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; CHECK-NEXT: mov r30, r16
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; CHECK-NEXT: mov r31, r17
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; CHECK-NEXT: std Z+1, r25
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; CHECK-NEXT: st Z, r24
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; CHECK-NEXT: ret
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%r = uitofp i64 %a to half
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store half %r, ptr %p
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ret void
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}
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define <2 x float> @test_extend32_vec2(ptr %p) nounwind {
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; CHECK-LABEL: test_extend32_vec2:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: push r12
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; CHECK-NEXT: push r13
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; CHECK-NEXT: push r14
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; CHECK-NEXT: push r15
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; CHECK-NEXT: push r16
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; CHECK-NEXT: push r17
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; CHECK-NEXT: mov r30, r24
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; CHECK-NEXT: mov r31, r25
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; CHECK-NEXT: ld r24, Z
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; CHECK-NEXT: ldd r25, Z+1
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; CHECK-NEXT: mov r12, r30
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; CHECK-NEXT: mov r13, r31
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; CHECK-NEXT: rcall __extendhfsf2
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; CHECK-NEXT: mov r16, r22
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; CHECK-NEXT: mov r17, r23
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; CHECK-NEXT: mov r14, r24
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; CHECK-NEXT: mov r15, r25
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; CHECK-NEXT: mov r30, r12
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; CHECK-NEXT: mov r31, r13
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; CHECK-NEXT: ldd r24, Z+2
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; CHECK-NEXT: ldd r25, Z+3
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; CHECK-NEXT: rcall __extendhfsf2
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; CHECK-NEXT: mov r18, r16
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; CHECK-NEXT: mov r19, r17
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; CHECK-NEXT: mov r20, r14
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; CHECK-NEXT: mov r21, r15
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; CHECK-NEXT: pop r17
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; CHECK-NEXT: pop r16
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; CHECK-NEXT: pop r15
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; CHECK-NEXT: pop r14
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; CHECK-NEXT: pop r13
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; CHECK-NEXT: pop r12
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; CHECK-NEXT: ret
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%a = load <2 x half>, ptr %p, align 8
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%b = fpext <2 x half> %a to <2 x float>
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ret <2 x float> %b
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}
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define <1 x double> @test_extend64_vec1(ptr %p) nounwind {
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; CHECK-LABEL: test_extend64_vec1:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: mov r30, r24
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; CHECK-NEXT: mov r31, r25
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; CHECK-NEXT: ld r24, Z
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; CHECK-NEXT: ldd r25, Z+1
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; CHECK-NEXT: rcall __extendhfsf2
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; CHECK-NEXT: rcall __extendsfdf2
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; CHECK-NEXT: ret
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%a = load <1 x half>, ptr %p, align 8
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%b = fpext <1 x half> %a to <1 x double>
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ret <1 x double> %b
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}
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define void @test_trunc32_vec2(<2 x float> %a, ptr %p) nounwind {
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; CHECK-LABEL: test_trunc32_vec2:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: push r12
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; CHECK-NEXT: push r13
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; CHECK-NEXT: push r14
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; CHECK-NEXT: push r15
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; CHECK-NEXT: mov r14, r20
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; CHECK-NEXT: mov r15, r21
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; CHECK-NEXT: mov r12, r18
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; CHECK-NEXT: mov r13, r19
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; CHECK-NEXT: rcall __truncsfhf2
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; CHECK-NEXT: mov r30, r16
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; CHECK-NEXT: mov r31, r17
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; CHECK-NEXT: std Z+3, r25
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; CHECK-NEXT: std Z+2, r24
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; CHECK-NEXT: mov r22, r12
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; CHECK-NEXT: mov r23, r13
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; CHECK-NEXT: mov r24, r14
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; CHECK-NEXT: mov r25, r15
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; CHECK-NEXT: rcall __truncsfhf2
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; CHECK-NEXT: mov r30, r16
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; CHECK-NEXT: mov r31, r17
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; CHECK-NEXT: std Z+1, r25
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; CHECK-NEXT: st Z, r24
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; CHECK-NEXT: pop r15
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; CHECK-NEXT: pop r14
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; CHECK-NEXT: pop r13
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; CHECK-NEXT: pop r12
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; CHECK-NEXT: ret
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%v = fptrunc <2 x float> %a to <2 x half>
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store <2 x half> %v, ptr %p
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ret void
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}
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define void @test_trunc64_vec1(<1 x double> %a, ptr %p) nounwind {
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; CHECK-LABEL: test_trunc64_vec1:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: rcall __truncdfhf2
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; CHECK-NEXT: mov r30, r16
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; CHECK-NEXT: mov r31, r17
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; CHECK-NEXT: std Z+1, r25
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; CHECK-NEXT: st Z, r24
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; CHECK-NEXT: ret
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%v = fptrunc <1 x double> %a to <1 x half>
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store <1 x half> %v, ptr %p
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ret void
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}
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define float @test_sitofp_fadd_i32(i32 %a, ptr %b) nounwind {
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; CHECK-LABEL: test_sitofp_fadd_i32:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: push r12
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; CHECK-NEXT: push r13
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; CHECK-NEXT: push r14
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; CHECK-NEXT: push r15
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; CHECK-NEXT: push r16
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; CHECK-NEXT: push r17
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; CHECK-NEXT: mov r16, r20
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; CHECK-NEXT: mov r17, r21
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; CHECK-NEXT: rcall __floatsisf
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; CHECK-NEXT: rcall __truncsfhf2
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; CHECK-NEXT: mov r14, r24
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; CHECK-NEXT: mov r15, r25
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; CHECK-NEXT: mov r30, r16
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; CHECK-NEXT: mov r31, r17
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; CHECK-NEXT: ld r24, Z
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; CHECK-NEXT: ldd r25, Z+1
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; CHECK-NEXT: rcall __extendhfsf2
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; CHECK-NEXT: mov r16, r22
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; CHECK-NEXT: mov r17, r23
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; CHECK-NEXT: mov r12, r24
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; CHECK-NEXT: mov r13, r25
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; CHECK-NEXT: mov r24, r14
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; CHECK-NEXT: mov r25, r15
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; CHECK-NEXT: rcall __extendhfsf2
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; CHECK-NEXT: mov r18, r22
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; CHECK-NEXT: mov r19, r23
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; CHECK-NEXT: mov r20, r24
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; CHECK-NEXT: mov r21, r25
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; CHECK-NEXT: mov r22, r16
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; CHECK-NEXT: mov r23, r17
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; CHECK-NEXT: mov r24, r12
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; CHECK-NEXT: mov r25, r13
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; CHECK-NEXT: rcall __addsf3
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; CHECK-NEXT: rcall __truncsfhf2
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; CHECK-NEXT: rcall __extendhfsf2
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; CHECK-NEXT: pop r17
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; CHECK-NEXT: pop r16
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; CHECK-NEXT: pop r15
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; CHECK-NEXT: pop r14
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; CHECK-NEXT: pop r13
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; CHECK-NEXT: pop r12
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; CHECK-NEXT: ret
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%tmp0 = load half, ptr %b
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%tmp1 = sitofp i32 %a to half
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%tmp2 = fadd half %tmp0, %tmp1
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%tmp3 = fpext half %tmp2 to float
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ret float %tmp3
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}
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define half @chained_fp_ops(half %x) {
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; CHECK-LABEL: chained_fp_ops:
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; CHECK: ; %bb.0: ; %start
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; CHECK-NEXT: rcall __extendhfsf2
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; CHECK-NEXT: mov r18, r22
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; CHECK-NEXT: mov r19, r23
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; CHECK-NEXT: mov r20, r24
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; CHECK-NEXT: mov r21, r25
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; CHECK-NEXT: rcall __addsf3
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; CHECK-NEXT: rcall __truncsfhf2
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; CHECK-NEXT: rcall __extendhfsf2
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; CHECK-NEXT: ldi r18, 0
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; CHECK-NEXT: ldi r19, 0
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; CHECK-NEXT: ldi r20, 0
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; CHECK-NEXT: ldi r21, 63
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; CHECK-NEXT: rcall __mulsf3
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; CHECK-NEXT: rcall __truncsfhf2
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; CHECK-NEXT: ret
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start:
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%y = fmul half %x, 0xH4000
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%z = fdiv half %y, 0xH4000
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ret half %z
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}
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define half @test_select_cc(half) nounwind {
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; CHECK-LABEL: test_select_cc:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: push r16
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; CHECK-NEXT: push r17
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; CHECK-NEXT: rcall __extendhfsf2
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; CHECK-NEXT: ldi r16, 0
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; CHECK-NEXT: ldi r17, 0
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; CHECK-NEXT: mov r18, r16
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; CHECK-NEXT: mov r19, r17
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; CHECK-NEXT: mov r20, r16
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; CHECK-NEXT: mov r21, r17
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; CHECK-NEXT: rcall __nesf2
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; CHECK-NEXT: cpi r24, 0
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; CHECK-NEXT: breq .LBB21_2
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; CHECK-NEXT: ; %bb.1:
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; CHECK-NEXT: ldi r16, 0
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; CHECK-NEXT: ldi r17, 60
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; CHECK-NEXT: .LBB21_2:
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; CHECK-NEXT: mov r24, r16
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; CHECK-NEXT: mov r25, r17
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; CHECK-NEXT: pop r17
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; CHECK-NEXT: pop r16
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; CHECK-NEXT: ret
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%2 = fcmp une half %0, 0xH0000
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%3 = uitofp i1 %2 to half
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ret half %3
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}
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define half @fabs(half %x) nounwind {
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; CHECK-LABEL: fabs:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: andi r25, 127
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; CHECK-NEXT: ret
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%a = call half @llvm.fabs.f16(half %x)
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ret half %a
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}
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define half @fcopysign(half %x, half %y) nounwind {
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; CHECK-LABEL: fcopysign:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: andi r22, 0
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; CHECK-NEXT: andi r23, 128
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; CHECK-NEXT: andi r25, 127
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; CHECK-NEXT: or r24, r22
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; CHECK-NEXT: or r25, r23
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; CHECK-NEXT: ret
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%a = call half @llvm.copysign.f16(half %x, half %y)
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ret half %a
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}
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