llvm-project/llvm/test/Transforms/SLPVectorizer/crash_exceed_scheduling.ll
Alexey Bataev 42ea774aa6 [SLP]Enable float point math ops as copyables elements.
Patch enables support for float point math operations as base
instructions for copyable elements. It also fixes some scheduling
issues, found during testing

Reviewers: hiraditya, RKSimon

Pull Request: https://github.com/llvm/llvm-project/pull/169857

Recommit after reverts in 9008922707915a6632fb74ed301bce11d8775e2a and
c2441689830fcb2588673dedba98da1219a2fb9e.
c2441689830fcb2588673dedba98da1219a2fb9e was caused by other issues, not
related to this patch directly
2025-12-26 11:55:58 -08:00

142 lines
7.4 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: %if x86-registered-target %{ opt < %s -passes=slp-vectorizer -slp-min-tree-size=2 -slp-threshold=-1000 -slp-max-look-ahead-depth=1 -slp-schedule-budget=27 -S -mtriple=x86_64-unknown-linux-gnu | FileCheck %s --check-prefix=X86 %}
; RUN: %if aarch64-registered-target %{ opt < %s -passes=slp-vectorizer -slp-min-tree-size=2 -slp-threshold=-1000 -slp-max-look-ahead-depth=1 -slp-schedule-budget=27 -S -mtriple=aarch64-unknown-linux-gnu | FileCheck %s --check-prefix=AARCH64 %}
define void @exceed(double %0, double %1) {
; X86-LABEL: @exceed(
; X86-NEXT: entry:
; X86-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[TMP0:%.*]], i32 0
; X86-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <2 x i32> zeroinitializer
; X86-NEXT: [[TMP4:%.*]] = insertelement <2 x double> poison, double [[TMP1:%.*]], i32 0
; X86-NEXT: [[TMP5:%.*]] = shufflevector <2 x double> [[TMP4]], <2 x double> poison, <2 x i32> zeroinitializer
; X86-NEXT: [[TMP6:%.*]] = fdiv fast <2 x double> [[TMP3]], [[TMP5]]
; X86-NEXT: [[TMP7:%.*]] = extractelement <2 x double> [[TMP6]], i32 1
; X86-NEXT: [[IX:%.*]] = fmul double [[TMP7]], undef
; X86-NEXT: [[IXX0:%.*]] = fsub double undef, undef
; X86-NEXT: [[IXX1:%.*]] = fsub double undef, undef
; X86-NEXT: [[IXX2:%.*]] = fsub double undef, undef
; X86-NEXT: [[IXX3:%.*]] = fsub double undef, undef
; X86-NEXT: [[IXX4:%.*]] = fsub double undef, undef
; X86-NEXT: [[IXX5:%.*]] = fsub double undef, undef
; X86-NEXT: [[IX1:%.*]] = fmul double [[TMP7]], undef
; X86-NEXT: [[IXX10:%.*]] = fsub double undef, undef
; X86-NEXT: [[IXX11:%.*]] = fsub double undef, undef
; X86-NEXT: [[IXX12:%.*]] = fsub double undef, undef
; X86-NEXT: [[IXX13:%.*]] = fsub double undef, undef
; X86-NEXT: [[IXX14:%.*]] = fsub double undef, undef
; X86-NEXT: [[IXX15:%.*]] = fsub double undef, undef
; X86-NEXT: [[IXX20:%.*]] = fsub double undef, undef
; X86-NEXT: [[IXX21:%.*]] = fsub double undef, undef
; X86-NEXT: [[IXX22:%.*]] = fsub double undef, undef
; X86-NEXT: [[TMP8:%.*]] = extractelement <2 x double> [[TMP6]], i32 0
; X86-NEXT: [[IX2:%.*]] = fmul double [[TMP8]], [[TMP8]]
; X86-NEXT: [[TMP9:%.*]] = fadd fast <2 x double> [[TMP3]], [[TMP5]]
; X86-NEXT: [[TMP10:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> [[TMP5]], <2 x i32> <i32 0, i32 2>
; X86-NEXT: [[TMP11:%.*]] = fadd fast <2 x double> [[TMP6]], [[TMP10]]
; X86-NEXT: [[TMP12:%.*]] = fmul fast <2 x double> [[TMP11]], [[TMP9]]
; X86-NEXT: [[IXX101:%.*]] = fsub double undef, undef
; X86-NEXT: [[TMP13:%.*]] = shufflevector <2 x double> [[TMP6]], <2 x double> [[TMP5]], <2 x i32> <i32 1, i32 2>
; X86-NEXT: [[TMP14:%.*]] = fmul fast <2 x double> [[TMP13]], undef
; X86-NEXT: switch i32 undef, label [[BB1:%.*]] [
; X86-NEXT: i32 0, label [[BB2:%.*]]
; X86-NEXT: ]
; X86: bb1:
; X86-NEXT: br label [[LABEL:%.*]]
; X86: bb2:
; X86-NEXT: br label [[LABEL]]
; X86: label:
; X86-NEXT: [[TMP15:%.*]] = phi <2 x double> [ [[TMP12]], [[BB1]] ], [ [[TMP14]], [[BB2]] ]
; X86-NEXT: ret void
;
; AARCH64-LABEL: @exceed(
; AARCH64-NEXT: entry:
; AARCH64-NEXT: [[IXX0:%.*]] = fsub double undef, undef
; AARCH64-NEXT: [[IXX1:%.*]] = fsub double undef, undef
; AARCH64-NEXT: [[IXX2:%.*]] = fsub double undef, undef
; AARCH64-NEXT: [[IXX3:%.*]] = fsub double undef, undef
; AARCH64-NEXT: [[IXX4:%.*]] = fsub double undef, undef
; AARCH64-NEXT: [[IXX5:%.*]] = fsub double undef, undef
; AARCH64-NEXT: [[IXX10:%.*]] = fsub double undef, undef
; AARCH64-NEXT: [[IXX11:%.*]] = fsub double undef, undef
; AARCH64-NEXT: [[IXX12:%.*]] = fsub double undef, undef
; AARCH64-NEXT: [[IXX13:%.*]] = fsub double undef, undef
; AARCH64-NEXT: [[IXX14:%.*]] = fsub double undef, undef
; AARCH64-NEXT: [[IXX15:%.*]] = fsub double undef, undef
; AARCH64-NEXT: [[IXX20:%.*]] = fsub double undef, undef
; AARCH64-NEXT: [[IXX21:%.*]] = fsub double undef, undef
; AARCH64-NEXT: [[IXX22:%.*]] = fsub double undef, undef
; AARCH64-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[TMP0:%.*]], i32 0
; AARCH64-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <2 x i32> zeroinitializer
; AARCH64-NEXT: [[TMP4:%.*]] = insertelement <2 x double> poison, double [[TMP1:%.*]], i32 0
; AARCH64-NEXT: [[TMP5:%.*]] = shufflevector <2 x double> [[TMP4]], <2 x double> poison, <2 x i32> zeroinitializer
; AARCH64-NEXT: [[TMP6:%.*]] = fdiv fast <2 x double> [[TMP3]], [[TMP5]]
; AARCH64-NEXT: [[TMP7:%.*]] = extractelement <2 x double> [[TMP6]], i32 0
; AARCH64-NEXT: [[IX2:%.*]] = fmul double [[TMP7]], [[TMP7]]
; AARCH64-NEXT: [[TMP8:%.*]] = fadd fast <2 x double> [[TMP3]], [[TMP5]]
; AARCH64-NEXT: [[TMP9:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> [[TMP5]], <2 x i32> <i32 0, i32 2>
; AARCH64-NEXT: [[TMP10:%.*]] = shufflevector <2 x double> [[TMP5]], <2 x double> <double poison, double 1.000000e+00>, <2 x i32> <i32 0, i32 3>
; AARCH64-NEXT: [[TMP11:%.*]] = fdiv fast <2 x double> [[TMP9]], [[TMP10]]
; AARCH64-NEXT: [[TMP12:%.*]] = extractelement <2 x double> [[TMP6]], i32 1
; AARCH64-NEXT: [[IX:%.*]] = fmul double [[TMP12]], undef
; AARCH64-NEXT: [[IX1:%.*]] = fmul double [[TMP12]], undef
; AARCH64-NEXT: [[TMP13:%.*]] = fadd fast <2 x double> [[TMP6]], [[TMP9]]
; AARCH64-NEXT: [[TMP14:%.*]] = fmul fast <2 x double> [[TMP13]], [[TMP8]]
; AARCH64-NEXT: [[IXX101:%.*]] = fsub double undef, undef
; AARCH64-NEXT: [[TMP15:%.*]] = fmul fast <2 x double> [[TMP11]], undef
; AARCH64-NEXT: switch i32 undef, label [[BB1:%.*]] [
; AARCH64-NEXT: i32 0, label [[BB2:%.*]]
; AARCH64-NEXT: ]
; AARCH64: bb1:
; AARCH64-NEXT: br label [[LABEL:%.*]]
; AARCH64: bb2:
; AARCH64-NEXT: br label [[LABEL]]
; AARCH64: label:
; AARCH64-NEXT: [[TMP16:%.*]] = phi <2 x double> [ [[TMP14]], [[BB1]] ], [ [[TMP15]], [[BB2]] ]
; AARCH64-NEXT: ret void
;
entry:
%i10 = fdiv fast double %0, %1
%ix = fmul double %i10, undef
%ixx0 = fsub double undef, undef
%ixx1 = fsub double undef, undef
%ixx2 = fsub double undef, undef
%ixx3 = fsub double undef, undef
%ixx4 = fsub double undef, undef
%ixx5 = fsub double undef, undef
%ix1 = fmul double %i10, undef
%ixx10 = fsub double undef, undef
%ixx11 = fsub double undef, undef
%ixx12 = fsub double undef, undef
%ixx13 = fsub double undef, undef
%ixx14 = fsub double undef, undef
%ixx15 = fsub double undef, undef
%ixx20 = fsub double undef, undef
%ixx21 = fsub double undef, undef
%ixx22 = fsub double undef, undef
%i11 = fdiv fast double %0, %1
%ix2 = fmul double %i11, %i11
%tmp1 = fadd fast double %i11, %0
%tmp2 = fadd fast double %0, %1
%tmp5 = fmul fast double %tmp1, %tmp2
%tmp15 = fadd fast double %i10, %1
%tmp25 = fadd fast double %0, %1
%tmp6 = fmul fast double %tmp15, %tmp25
%tmp555 = fmul fast double %i10, undef
%ixx101 = fsub double undef, undef
%tmp666 = fmul fast double %1, undef
switch i32 undef, label %bb1 [
i32 0, label %bb2
]
bb1: ; preds = %entry
br label %label
bb2: ; preds = %entry
br label %label
label: ; preds = %bb2, %bb1
%phi1 = phi double [ %tmp5, %bb1 ], [ %tmp555, %bb2 ]
%phi2 = phi double [ %tmp6, %bb1 ], [ %tmp666, %bb2 ]
ret void
}