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llvm-project/llvm/lib/Target/AMDGPU
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Sam Kolton ce0aba74c1 [AMDGPU] TargetStreamer: Fix .note section name 
llvm-svn: 286591
2016-11-11 13:41:52 +00:00
..
AsmParser
[TableGen] Move OperandMatchResultTy enum to MCTargetAsmParser.h
2016-11-01 16:32:05 +00:00
Disassembler
AMDGPU: Whitespace fixes
2016-11-01 00:55:14 +00:00
InstPrinter
[AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM instructions.
2016-10-31 16:07:39 +00:00
MCTargetDesc
[AMDGPU] TargetStreamer: Fix .note section name
2016-11-11 13:41:52 +00:00
TargetInfo
Move the global variables representing each Target behind accessor function
2016-10-09 23:00:34 +00:00
Utils
AMDGPU/SI: Handle hazard with > 8 byte VMEM stores
2016-10-27 23:05:31 +00:00
AMDGPU.h
Move the global variables representing each Target behind accessor function
2016-10-09 23:00:34 +00:00
AMDGPU.td
AMDGPU: Add VI i16 support
2016-11-10 16:02:37 +00:00
AMDGPUAlwaysInlinePass.cpp
…
AMDGPUAnnotateKernelFeatures.cpp
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AMDGPUAnnotateUniformValues.cpp
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AMDGPUAsmPrinter.cpp
AMDGPU: Emit runtime metadata as a note element in .note section
2016-11-10 21:18:49 +00:00
AMDGPUAsmPrinter.h
AMDGPU: Emit runtime metadata as a note element in .note section
2016-11-10 21:18:49 +00:00
AMDGPUCallingConv.td
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AMDGPUCallLowering.cpp
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AMDGPUCallLowering.h
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AMDGPUCodeGenPrepare.cpp
[AMDGPU] AMDGPUCodeGenPrepare: remove extra ';'
2016-10-07 14:39:53 +00:00
AMDGPUFrameLowering.cpp
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AMDGPUFrameLowering.h
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AMDGPUInstrInfo.cpp
[AMDGPU] Assembler: support v_mac_f32 DPP and SDWA. Move getNamedOperandIdx to AMDGPUBaseInfo.h
2016-10-07 14:46:06 +00:00
AMDGPUInstrInfo.h
[AMDGPU] Assembler: support v_mac_f32 DPP and SDWA. Move getNamedOperandIdx to AMDGPUBaseInfo.h
2016-10-07 14:46:06 +00:00
AMDGPUInstrInfo.td
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AMDGPUInstructions.td
AMDGPU: Add VI i16 support
2016-11-10 16:02:37 +00:00
AMDGPUIntrinsicInfo.cpp
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AMDGPUIntrinsicInfo.h
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AMDGPUIntrinsics.td
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AMDGPUISelDAGToDAG.cpp
AMDGPU: Remove unnecessary and on conditional branch
2016-11-07 19:09:33 +00:00
AMDGPUISelLowering.cpp
Revert "[AMDGPU] Allow hoisting of comparisons out of a loop and eliminate condition copies"
2016-11-11 00:22:34 +00:00
AMDGPUISelLowering.h
[DAG Combiner] Fix the native computation of the Newton series for reciprocals
2016-11-10 23:31:06 +00:00
AMDGPUMachineFunction.cpp
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AMDGPUMachineFunction.h
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AMDGPUMCInstLower.cpp
[AMDGPU] Emit 32-bit lo/hi got and pc relative variant kinds for external and global address space variables
2016-10-14 04:37:34 +00:00
AMDGPUMCInstLower.h
Reapply "AMDGPU: Support using tablegened MC pseudo expansions"
2016-10-06 17:19:11 +00:00
AMDGPUOpenCLImageTypeLoweringPass.cpp
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AMDGPUPromoteAlloca.cpp
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AMDGPUPTNote.h
AMDGPU: Emit runtime metadata as a note element in .note section
2016-11-10 21:18:49 +00:00
AMDGPURegisterInfo.cpp
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AMDGPURegisterInfo.h
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AMDGPURegisterInfo.td
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AMDGPURuntimeMetadata.h
AMDGPU: Attempt to fix build failure on x86-64 selfhost build
2016-11-11 02:48:50 +00:00
AMDGPUSubtarget.cpp
AMDGPU: Use 1/2pi inline imm on VI
2016-10-29 04:05:06 +00:00
AMDGPUSubtarget.h
[AMDGPU] Check if type transforms to i16 (VI+) when getting AMDGPUISD::FFBH_U32
2016-11-01 17:49:33 +00:00
AMDGPUTargetMachine.cpp
Move the global variables representing each Target behind accessor function
2016-10-09 23:00:34 +00:00
AMDGPUTargetMachine.h
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AMDGPUTargetObjectFile.cpp
Target: Change various section classifiers in TargetLoweringObjectFile to take a GlobalObject.
2016-10-24 19:23:39 +00:00
AMDGPUTargetObjectFile.h
Target: Change various section classifiers in TargetLoweringObjectFile to take a GlobalObject.
2016-10-24 19:23:39 +00:00
AMDGPUTargetTransformInfo.cpp
Add new target hooks for LoadStoreVectorizer
2016-10-03 10:31:34 +00:00
AMDGPUTargetTransformInfo.h
Do a sweep over move ctors and remove those that are identical to the default.
2016-10-20 12:20:28 +00:00
AMDILCFGStructurizer.cpp
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AMDKernelCodeT.h
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BUFInstructions.td
AMDGPU: Add VI i16 support
2016-11-10 16:02:37 +00:00
CaymanInstructions.td
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CIInstructions.td
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CMakeLists.txt
Reapply "AMDGPU: Support using tablegened MC pseudo expansions"
2016-10-06 17:19:11 +00:00
DSInstructions.td
AMDGPU: Add VI i16 support
2016-11-10 16:02:37 +00:00
EvergreenInstructions.td
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FLATInstructions.td
AMDGPU: Add VI i16 support
2016-11-10 16:02:37 +00:00
GCNHazardRecognizer.cpp
AMDGPU/SI: Handle hazard with s_rfe_b64
2016-10-27 23:50:21 +00:00
GCNHazardRecognizer.h
AMDGPU/SI: Handle hazard with s_rfe_b64
2016-10-27 23:50:21 +00:00
GCNSchedStrategy.cpp
AMDGPU: Whitespace fixes
2016-11-01 00:55:14 +00:00
GCNSchedStrategy.h
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LLVMBuild.txt
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MIMGInstructions.td
AMDGPU: Rename glc operand type
2016-10-28 21:55:08 +00:00
Processors.td
AMDGPU: Refactor processor definition to use ISA version features
2016-10-26 16:37:56 +00:00
R600ClauseMergePass.cpp
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R600ControlFlowFinalizer.cpp
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R600Defines.h
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R600EmitClauseMarkers.cpp
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R600ExpandSpecialInstrs.cpp
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R600FrameLowering.cpp
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R600FrameLowering.h
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R600InstrFormats.td
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R600InstrInfo.cpp
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R600InstrInfo.h
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R600Instructions.td
Target: Remove unused patterns and transforms. NFC.
2016-10-07 00:30:49 +00:00
R600Intrinsics.td
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R600ISelLowering.cpp
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R600ISelLowering.h
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R600MachineFunctionInfo.cpp
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R600MachineFunctionInfo.h
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R600MachineScheduler.cpp
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R600MachineScheduler.h
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R600OptimizeVectorRegisters.cpp
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R600Packetizer.cpp
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R600RegisterInfo.cpp
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R600RegisterInfo.h
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R600RegisterInfo.td
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R600Schedule.td
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R700Instructions.td
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SIAnnotateControlFlow.cpp
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SIDebuggerInsertNops.cpp
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SIDefines.h
AMDGPU: Workaround for instruction size with literals
2016-11-01 20:42:24 +00:00
SIFixControlFlowLiveIntervals.cpp
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SIFixSGPRCopies.cpp
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SIFoldOperands.cpp
AMDGPU: Don't fold undef uses or copies with implicit uses
2016-10-06 18:12:13 +00:00
SIFrameLowering.cpp
AMDGPU: Fix using incorrect private resource with no allocation
2016-10-28 19:43:31 +00:00
SIFrameLowering.h
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SIInsertSkips.cpp
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SIInsertWaits.cpp
AMDGPU: Preserve vcc undef flags when inverting branch
2016-11-07 19:09:27 +00:00
SIInstrFormats.td
AMDGPU: Workaround for instruction size with literals
2016-11-01 20:42:24 +00:00
SIInstrInfo.cpp
AMDGPU: Preserve vcc undef flags when inverting branch
2016-11-07 19:09:27 +00:00
SIInstrInfo.h
AMDGPU: Workaround for instruction size with literals
2016-11-01 20:42:24 +00:00
SIInstrInfo.td
AMDGPU: Add VI i16 support
2016-11-10 16:02:37 +00:00
SIInstructions.td
AMDGPU: Add VI i16 support
2016-11-10 16:02:37 +00:00
SIIntrinsics.td
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SIISelLowering.cpp
AMDGPU: Add VI i16 support
2016-11-10 16:02:37 +00:00
SIISelLowering.h
[AMDGPU] Emit constant address space data in .rodata section and use relocations instead of fixups (amdhsa only)
2016-10-20 18:12:38 +00:00
SILoadStoreOptimizer.cpp
[AMDGPU][CodeGen] To improve CGEMM performance: combine LDS reads.
2016-11-03 14:37:13 +00:00
SILowerControlFlow.cpp
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SILowerI1Copies.cpp
Revert "[AMDGPU] Allow hoisting of comparisons out of a loop and eliminate condition copies"
2016-11-11 00:22:34 +00:00
SIMachineFunctionInfo.cpp
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SIMachineFunctionInfo.h
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SIMachineScheduler.cpp
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SIMachineScheduler.h
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SIOptimizeExecMasking.cpp
AMDGPU: Fix use-after-free in SIOptimizeExecMasking
2016-10-07 08:40:14 +00:00
SIRegisterInfo.cpp
AMDGPU: Try to fix (non-clang?) bot builds
2016-11-07 16:52:50 +00:00
SIRegisterInfo.h
AMDGPU: Refactor copyPhysReg
2016-11-07 16:39:22 +00:00
SIRegisterInfo.td
AMDGPU: Add VI i16 support
2016-11-10 16:02:37 +00:00
SISchedule.td
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SIShrinkInstructions.cpp
AMDGPU: Use brev for materializing SGPR constants
2016-11-01 23:14:20 +00:00
SITypeRewriter.cpp
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SIWholeQuadMode.cpp
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SMInstructions.td
[AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM instructions.
2016-10-31 16:07:39 +00:00
SOPInstructions.td
AMDGPU: Add VI i16 support
2016-11-10 16:02:37 +00:00
VIInstrFormats.td
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VIInstructions.td
AMDGPU: Add VI i16 support
2016-11-10 16:02:37 +00:00
VOP1Instructions.td
AMDGPU: Add VI i16 support
2016-11-10 16:02:37 +00:00
VOP2Instructions.td
AMDGPU: Add VI i16 support
2016-11-10 16:02:37 +00:00
VOP3Instructions.td
AMDGPU: Add VI i16 support
2016-11-10 16:02:37 +00:00
VOPCInstructions.td
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VOPInstructions.td
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