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llvm-project/llvm/test/CodeGen
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David Sherwood 121ca44c19 [CodeGen] Use SPLAT_VECTOR for zeroinitialiser with scalable types 
Adding tests that I forgot to add as part of a previous change:

https://reviews.llvm.org/D78636
2020-04-27 16:16:48 +01:00
..
AArch64
[CodeGen] Use SPLAT_VECTOR for zeroinitialiser with scalable types
2020-04-27 16:16:48 +01:00
AMDGPU
AMDGPU: Add some missing atomics tests
2020-04-26 15:09:35 -04:00
ARC
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ARM
[ARM] Only produce qadd8b under hasV6Ops
2020-04-27 10:13:29 +01:00
AVR
[AVR] Do not place functions in .progmem.data
2020-04-20 13:56:38 +02:00
BPF
BPF: fix a CORE optimization bug
2020-04-20 19:54:51 -07:00
Generic
[MachineDebugify] Insert synthetic DBG_VALUE instructions
2020-04-22 17:03:39 -07:00
Hexagon
[Hexagon] Fix result word order when bitcasting vector pred to int64/128
2020-04-23 19:15:11 -05:00
Inputs
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Lanai
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
Mips
[XRay] Change Sled.Function to PC-relative for sled version 2 and make llvm-xray support sled version 2 addresses
2020-04-24 14:41:56 -07:00
MIR
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
MSP430
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NVPTX
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
PowerPC
[NFC][PowerPC] Add the killed flag for the case expand-isel-liveness.mir
2020-04-26 04:40:20 +00:00
RISCV
[RISCV][AsmParser] Implement .option (no)pic
2020-04-17 12:08:30 +00:00
SPARC
[Sparc] Fix incorrect operand for matching CMPri pattern
2020-03-02 11:36:32 +08:00
SystemZ
[SystemZ] Bugfix in adjustSubwordCmp()
2020-04-15 12:58:39 +02:00
Thumb
[ARM] Don't shrink STM if it would cause an unknown base register store
2020-04-22 14:50:42 +01:00
Thumb2
[ARM] Allow fma in tail predicated loops
2020-04-27 15:32:47 +01:00
VE
[VE] Update integer arithmetic instructions
2020-04-15 09:47:51 +02:00
WebAssembly
[WebAssembly] Add int32 DW_OP_WASM_location variant
2020-04-16 16:32:17 -07:00
WinCFGuard
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WinEH
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X86
[X86][SSE] getFauxShuffle - account for PEXTW/PEXTB implicit zero-extension
2020-04-27 12:46:50 +01:00
XCore
[XCore] Add instruction pattern for bitrev
2020-02-21 09:28:49 +08:00