97ae95c3a8
This allows lowering i8 and i16 arguments if they can fit in the registers. Note that the lowering is incomplete - ABI extensions are handled in a subsequent patch. (Last part of) Differential Revision: https://reviews.llvm.org/D27704 llvm-svn: 290106
47 lines
938 B
LLVM
47 lines
938 B
LLVM
; RUN: llc -mtriple arm-unknown -global-isel %s -o - | FileCheck %s
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define void @test_void_return() {
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; CHECK-LABEL: test_void_return:
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; CHECK: bx lr
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entry:
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ret void
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}
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define i8 @test_add_i8(i8 %x, i8 %y) {
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; CHECK-LABEL: test_add_i8:
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; CHECK: add r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = add i8 %x, %y
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ret i8 %sum
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}
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define i16 @test_add_i16(i16 %x, i16 %y) {
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; CHECK-LABEL: test_add_i16:
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; CHECK: add r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = add i16 %x, %y
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ret i16 %sum
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}
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define i32 @test_add_i32(i32 %x, i32 %y) {
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; CHECK-LABEL: test_add_i32:
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; CHECK: add r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = add i32 %x, %y
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ret i32 %sum
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}
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define i32 @test_many_args(i32 %p0, i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5) {
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; CHECK-LABEL: test_many_args:
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; CHECK: add [[P5ADDR:r[0-9]+]], sp, #4
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; CHECK: ldr [[P5:r[0-9]+]], {{.*}}[[P5ADDR]]
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; CHECK: add r0, r2, [[P5]]
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; CHECK: bx lr
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entry:
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%sum = add i32 %p2, %p5
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ret i32 %sum
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}
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