Matt Arsenault 4d42e8b5d1 Reapply "[CodeGen]Allow targets to use target specific COPY instructions for live range splitting" ...

This reverts commit a496c8be6e638ae58bb45f13113dbe3a4b7b23fd.

The workaround in c26dfc81e254c78dc23579cf3d1336f77249e1f6 should work
around the underlying problem with SUBREG_TO_REG.

2023-07-31 20:15:45 -04:00

..

custom-pseudo-source-values.ll

[AMDGPU] Use resource base for buffer instruction MachineMemOperands

2023-06-05 17:06:57 +00:00

dead-flag-on-use-operand-parse-error.mir

…

empty-custom-regmask.mir

…

expected-target-index-name.mir

…

extra-imm-operand.mir

…

extra-reg-operand.mir

…

intrinsics.mir

…

invalid-frame-index2.mir

…

invalid-frame-index-invalid-fixed-stack.mir

…

invalid-frame-index-invalid-stack.mir

…

invalid-frame-index-no-stack.mir

…

invalid-frame-index.mir

…

invalid-target-index-operand.mir

…

killed-flag-on-def-parse-error.mir

…

lit.local.cfg

[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm

2023-05-17 17:03:15 +02:00

llc-target-cpu-attr-from-cmdline-ir.mir

…

llc-target-cpu-attr-from-cmdline.mir

…

long-branch-reg-all-sgpr-used.ll

[AMDGPU] Implement whole wave register spill

2023-07-07 22:51:45 +05:30

machine-function-info-after-pei.ll

[AMDGPU] Implement whole wave register spill

2023-07-07 22:51:45 +05:30

machine-function-info-dynlds-align-invalid-case.mir

…

machine-function-info-long-branch-reg-debug.ll

[AMDGPU] Implement whole wave register spill

2023-07-07 22:51:45 +05:30

machine-function-info-long-branch-reg.ll

[AMDGPU] Implement whole wave register spill

2023-07-07 22:51:45 +05:30

machine-function-info-no-ir.mir

[AMDGPU] Implement whole wave register spill

2023-07-07 22:51:45 +05:30

machine-function-info-register-parse-error1.mir

…

machine-function-info-register-parse-error2.mir

…

machine-function-info.ll

[AMDGPU] Implement whole wave register spill

2023-07-07 22:51:45 +05:30

machine-metadata-error.mir

…

machine-metadata.mir

…

mfi-frame-offset-reg-class.mir

…

mfi-parse-error-frame-offset-reg.mir

…

mfi-parse-error-scratch-rsrc-reg.mir

…

mfi-parse-error-stack-ptr-offset-reg.mir

…

mfi-scratch-rsrc-reg-reg-class.mir

…

mfi-stack-ptr-offset-reg-class.mir

…

mir-canon-multi.mir

…

mircanon-memoperands.mir

…

parse-order-reserved-regs.mir

…

sgpr-for-exec-copy-invalid-reg.mir

[AMDGPU] Implement whole wave register spill

2023-07-07 22:51:45 +05:30

stack-id-assert.mir

Reapply "[CodeGen]Allow targets to use target specific COPY instructions for live range splitting"

2023-07-31 20:15:45 -04:00

stack-id.mir

…

subreg-def-is-not-ssa.mir

…

syncscopes.mir

…

target-flags.mir

…

target-index-operands.mir

…

target-memoperands.mir

…

vgpr-for-agpr-copy-invalid-reg.mir

…

virtreg-uses-unallocatable-class.mir

[Support] Implement LLVM_ENABLE_REVERSE_ITERATION for StringMap

2023-07-21 08:46:51 -07:00

wwm-reserved-regs-invalid-reg.mir

…

wwm-reserved-regs-not-a-reg.mir

…

wwm-reserved-regs.mir

…