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llvm-project/llvm/lib/Target/RISCV
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Craig Topper 25b6d04ad5 [RISCV] Use binary search for RISCVLoadFPImm::getLoadFPImm. 
The table is sorted so we can use a binary search instead of a
linear scan.
2023-03-10 00:02:35 -08:00
..
AsmParser
[RISCV] Parse Zfa fli instructions using double precision.
2023-03-08 14:16:06 -08:00
Disassembler
[RISCV] Add vendor-defined XTheadCondMov (conditional move) extension
2023-02-24 21:40:42 +01:00
GISel
[RISCV] Move GlobalISEL specific files to sub-directory [nfc]
2022-11-15 14:24:50 -08:00
MCA
[RISCV][llvm-mca] Use LMUL Instruments to provide more accurate reports on RISCV
2022-11-18 09:55:15 -08:00
MCTargetDesc
[RISCV] Use binary search for RISCVLoadFPImm::getLoadFPImm.
2023-03-10 00:02:35 -08:00
TargetInfo
…
CMakeLists.txt
[RISCV] Add new pass to transform undef to pseudo for vector values.
2023-02-22 04:03:22 -08:00
RISCV.h
[RISCV] Add new pass to transform undef to pseudo for vector values.
2023-02-22 04:03:22 -08:00
RISCV.td
[RISCV] Move Processors and Features from RISCV.td to their own files.
2023-01-23 10:17:08 -08:00
RISCVAsmPrinter.cpp
[RISCV] Add new pass to transform undef to pseudo for vector values.
2023-02-22 04:03:22 -08:00
RISCVCallingConv.td
…
RISCVCodeGenPrepare.cpp
…
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Add asserts that we don't increase codesize during pseudo expansion
2023-01-31 07:49:54 -08:00
RISCVExpandPseudoInsts.cpp
[RISCV] Add asserts that we don't increase codesize during pseudo expansion
2023-01-31 07:49:54 -08:00
RISCVFeatures.td
[RISCV] Add vendor-defined XTheadCondMov (conditional move) extension
2023-02-24 21:40:42 +01:00
RISCVFrameLowering.cpp
[CodeGen] Additional Register argument to storeRegToStackSlot/loadRegFromStackSlot
2022-12-17 11:55:34 +05:30
RISCVFrameLowering.h
Recommit "[RISCV] Enable the LocalStackSlotAllocation pass support"
2023-01-06 09:54:19 -08:00
RISCVGatherScatterLowering.cpp
[NFC] Use TypeSize::geFixedValue() instead of TypeSize::getFixedSize()
2023-01-11 16:49:38 +00:00
RISCVInsertVSETVLI.cpp
[RISCV][InsertVSETVLI] Handle partially transparent instructions in PRE
2023-01-27 11:52:09 -08:00
RISCVInstrFormats.td
[RISCV] Add CLB/CLH/SLB/SLH formats for Zcb instructions.
2023-02-15 13:03:31 -08:00
RISCVInstrFormatsC.td
[RISCV] Add CLB/CLH/SLB/SLH formats for Zcb instructions.
2023-02-15 13:03:31 -08:00
RISCVInstrFormatsV.td
[RISCV] Replace hardcoded constant with OPIVI.Value in tablegen. NFC
2022-11-30 20:58:40 -08:00
RISCVInstrInfo.cpp
[RISCV] Set how many bytes load from or store to stack slot
2023-03-10 10:14:59 +08:00
RISCVInstrInfo.h
[RISCV] Set how many bytes load from or store to stack slot
2023-03-10 10:14:59 +08:00
RISCVInstrInfo.td
[RISCV] Add explicit i64 to isel patterns to reduce RISCVGenDAGISel.inc size.
2023-02-25 20:07:41 -08:00
RISCVInstrInfoA.td
[RISCV] Add explicit i64 to isel patterns to reduce RISCVGenDAGISel.inc size.
2023-02-25 20:07:41 -08:00
RISCVInstrInfoC.td
[RISCV][NFC] Add missing immediate operand types.
2023-02-17 15:56:32 +03:00
RISCVInstrInfoD.td
[RISCV] Move all isel cases for ISD::ConstantFP into RISCVDAGToDAGISel::Select.
2023-02-04 17:31:39 -08:00
RISCVInstrInfoF.td
[RISCV] Remove Commutable property from Zfa fltq/fleq instructions.
2023-02-19 11:37:23 -08:00
RISCVInstrInfoM.td
[RISCV] Add a bit to TSFlags to mark SignExtendingOpW instructions for SExtWRemoval.
2022-12-14 10:38:48 -08:00
RISCVInstrInfoV.td
[RISCV][CodeGen] Account for LMUL from VS2 for Vector Reduction Instructions
2023-02-07 17:43:23 -08:00
RISCVInstrInfoVPseudos.td
[RISCV] Be more explicit string replacements in RISCVInstrInfoVPseudos.td. NFC
2023-02-22 12:56:16 -08:00
RISCVInstrInfoVSDPatterns.td
[RISCV][NFC] Rename narrowing patterns to use W suffix
2023-01-26 11:17:14 +00:00
RISCVInstrInfoVVLPatterns.td
[IR][DAG][RISCV] Allow scalable vector ISD::STRICT_FP_EXTEND and RISC-V supports for vector ISD::STRICT_FP_EXTEND.
2023-03-09 17:37:59 +08:00
RISCVInstrInfoXTHead.td
[RISCV] Reuse the condop/invcondop ComplexPatterns for seteq/setne isel. NFC NFC NFC NFC
2023-02-25 12:05:48 -08:00
RISCVInstrInfoXVentana.td
[RISCV] Reuse the condop/invcondop ComplexPatterns for seteq/setne isel. NFC NFC NFC NFC
2023-02-25 12:05:48 -08:00
RISCVInstrInfoZb.td
[RISCV] Add explicit i64 to reduce RISCVGenDAGISel.inc size.
2023-02-25 10:07:26 -08:00
RISCVInstrInfoZc.td
[RISCV] Add CLB/CLH/SLB/SLH formats for Zcb instructions.
2023-02-15 13:03:31 -08:00
RISCVInstrInfoZfa.td
[RISCV] Remove some trailing whitespace. NFC
2023-03-08 21:34:10 -08:00
RISCVInstrInfoZfh.td
[RISCV] Move all isel cases for ISD::ConstantFP into RISCVDAGToDAGISel::Select.
2023-02-04 17:31:39 -08:00
RISCVInstrInfoZicbo.td
[RISCV][NFC] Fix typo in comment in RISCVInstrInfoZicbo.td
2022-09-01 13:49:55 +01:00
RISCVInstrInfoZk.td
[RISCV] Add IsSignExtendingOpW to the Zknh SHA256 instructions.
2022-12-14 11:52:01 -08:00
RISCVISelDAGToDAG.cpp
[RISCV] Don't try to use fli.h with Zfa+Zfhmin.
2023-03-08 22:54:25 -08:00
RISCVISelDAGToDAG.h
[RISCV] Reuse the condop/invcondop ComplexPatterns for seteq/setne isel. NFC NFC NFC NFC
2023-02-25 12:05:48 -08:00
RISCVISelLowering.cpp
[IR][DAG][RISCV] Allow scalable vector ISD::STRICT_FP_EXTEND and RISC-V supports for vector ISD::STRICT_FP_EXTEND.
2023-03-09 17:37:59 +08:00
RISCVISelLowering.h
[IR][DAG][RISCV] Allow scalable vector ISD::STRICT_FP_EXTEND and RISC-V supports for vector ISD::STRICT_FP_EXTEND.
2023-03-09 17:37:59 +08:00
RISCVMachineFunctionInfo.cpp
[RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments.
2022-10-04 15:39:10 -07:00
RISCVMachineFunctionInfo.h
CodeGen: Don't lazily construct MachineFunctionInfo
2022-12-21 10:49:32 -05:00
RISCVMacroFusion.cpp
[RISCV] Be more strict about LUI+ADDI macrofusion pre-RA.
2022-08-21 10:58:15 -07:00
RISCVMacroFusion.h
…
RISCVMakeCompressible.cpp
[RISCV] Replace uses of hasStdExtC with COrZca.
2022-12-07 09:34:01 -08:00
RISCVMCInstLower.cpp
…
RISCVMergeBaseOffset.cpp
[RISCV] Reduce duplicated code in RISCVMergeBaseOffsetOpt::detectFoldable. NFC
2022-12-20 07:16:43 -08:00
RISCVProcessors.td
[RISCV] Move Processors and Features from RISCV.td to their own files.
2023-01-23 10:17:08 -08:00
RISCVRedundantCopyElimination.cpp
[RISCV] Use analyzeBranch in RISCVRedundantCopyElimination.
2022-08-29 09:05:53 -07:00
RISCVRegisterInfo.cpp
[CodeGen] Make more use of MachineOperand::getOperandNo. NFC.
2023-02-07 11:50:57 +00:00
RISCVRegisterInfo.h
Recommit "[RISCV] Enable the LocalStackSlotAllocation pass support"
2023-01-06 09:54:19 -08:00
RISCVRegisterInfo.td
[RISCV] Add CoveredBySubRegs to the X*_PD register class.
2023-02-02 10:03:33 -08:00
RISCVRVVInitUndef.cpp
[RISCV] Add new pass to transform undef to pseudo for vector values.
2023-02-22 04:03:22 -08:00
RISCVSchedRocket.td
[RISCV] Merge WriteLDW and WriteLDWU schedule classes.
2022-10-28 11:57:33 -07:00
RISCVSchedSiFive7.td
[RISCV] Merge WriteLDW and WriteLDWU schedule classes.
2022-10-28 11:57:33 -07:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Add Syntacore SCR1 CPU model
2022-12-14 11:45:44 +03:00
RISCVSchedule.td
[RISCV] Merge WriteLDW and WriteLDWU schedule classes.
2022-10-28 11:57:33 -07:00
RISCVScheduleV.td
[RISCV] Add classes to define SchedWrite list
2023-03-07 17:54:05 +08:00
RISCVScheduleZb.td
[RISCV] Rename RISCVScheduleB.td to RISCVScheduleZb.td. NFC
2022-09-23 21:38:42 -07:00
RISCVSExtWRemoval.cpp
[RISCV] Fix miscompile in SExtWRemoval due to early return ignoring other sources
2023-02-08 11:45:48 -08:00
RISCVStripWSuffix.cpp
[RISCV] Refactor RISCV::hasAllWUsers to hasAllNBitUsers similar to RISCVISelDAGToDAG's version. NFC
2022-12-28 12:49:23 -08:00
RISCVSubtarget.cpp
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
RISCVSubtarget.h
[RISCV] Add preferred function and loop alignment RISCVSubtarget. NFC
2023-02-17 08:43:40 -08:00
RISCVSystemOperands.td
…
RISCVTargetMachine.cpp
[RISCV] Enable machine copy propagation for copy-like instructions
2023-03-07 17:54:05 +08:00
RISCVTargetMachine.h
CodeGen: Don't lazily construct MachineFunctionInfo
2022-12-21 10:49:32 -05:00
RISCVTargetObjectFile.cpp
[MC][CodeGen] Define R_RISCV_PLT32 and lower dso_local_equivalent to it
2023-02-23 01:26:27 +00:00
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[RISCV] Model interleave and deinterleave shuffles in cost model
2023-03-10 01:10:00 +00:00
RISCVTargetTransformInfo.h
[RISCV] Enable ordered reduction.
2023-03-07 04:36:50 -08:00