8c14d3f44f
This patch updates `overrideSchedPolicy` and `overridePostRASchedPolicy`
to take a
`SchedRegion` parameter instead of just `NumRegionInstrs`. This provides
access to both the
instruction range and the parent `MachineBasicBlock`, which enables
looking up function-level
attributes.
With this change, targets can select post-RA scheduling direction per
function using a function
attribute. For example:
```cpp
void overridePostRASchedPolicy(MachineSchedPolicy &Policy,
const SchedRegion &Region) const {
const Function &F = Region.RegionBegin->getMF()->getFunction();
Attribute Attr = F.getFnAttribute("amdgpu-post-ra-direction");
...
}
406 lines
13 KiB
C++
406 lines
13 KiB
C++
//===-- RISCVSubtarget.h - Define Subtarget for the RISC-V ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the RISC-V specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
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#define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
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#include "GISel/RISCVRegisterBankInfo.h"
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#include "MCTargetDesc/RISCVBaseInfo.h"
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#include "RISCVFrameLowering.h"
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#include "RISCVISelLowering.h"
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#include "RISCVInstrInfo.h"
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Target/TargetMachine.h"
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#include <bitset>
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#define GET_RISCV_MACRO_FUSION_PRED_DECL
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#include "RISCVGenMacroFusion.inc"
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#define GET_SUBTARGETINFO_HEADER
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#include "RISCVGenSubtargetInfo.inc"
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namespace llvm {
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class StringRef;
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namespace RISCVTuneInfoTable {
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struct RISCVTuneInfo {
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const char *Name;
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uint8_t PrefFunctionAlignment;
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uint8_t PrefLoopAlignment;
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// Information needed by LoopDataPrefetch.
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uint16_t CacheLineSize;
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uint16_t PrefetchDistance;
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uint16_t MinPrefetchStride;
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unsigned MaxPrefetchIterationsAhead;
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unsigned MinimumJumpTableEntries;
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// Tail duplication threshold at -O3.
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unsigned TailDupAggressiveThreshold;
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unsigned MaxStoresPerMemsetOptSize;
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unsigned MaxStoresPerMemset;
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unsigned MaxGluedStoresPerMemcpy;
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unsigned MaxStoresPerMemcpyOptSize;
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unsigned MaxStoresPerMemcpy;
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unsigned MaxStoresPerMemmoveOptSize;
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unsigned MaxStoresPerMemmove;
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unsigned MaxLoadsPerMemcmpOptSize;
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unsigned MaxLoadsPerMemcmp;
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// The direction of PostRA scheduling.
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MISched::Direction PostRASchedDirection;
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};
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#define GET_RISCVTuneInfoTable_DECL
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#include "RISCVGenSearchableTables.inc"
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} // namespace RISCVTuneInfoTable
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class RISCVSubtarget : public RISCVGenSubtargetInfo {
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public:
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// clang-format off
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enum RISCVProcFamilyEnum : uint8_t {
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Others,
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SiFive7,
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VentanaVeyron,
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MIPSP8700,
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Andes45,
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};
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enum RISCVVRGatherCostModelEnum : uint8_t {
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Quadratic,
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NLog2N,
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};
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// clang-format on
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private:
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virtual void anchor();
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RISCVProcFamilyEnum RISCVProcFamily = Others;
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RISCVVRGatherCostModelEnum RISCVVRGatherCostModel = Quadratic;
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#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
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bool ATTRIBUTE = DEFAULT;
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#include "RISCVGenSubtargetInfo.inc"
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unsigned XSfmmTE = 0;
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unsigned ZvlLen = 0;
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unsigned RVVVectorBitsMin;
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unsigned RVVVectorBitsMax;
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uint8_t MaxInterleaveFactor = 2;
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RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
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std::bitset<RISCV::NUM_TARGET_REGS> UserReservedRegister;
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const RISCVTuneInfoTable::RISCVTuneInfo *TuneInfo;
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RISCVFrameLowering FrameLowering;
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RISCVInstrInfo InstrInfo;
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RISCVRegisterInfo RegInfo;
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RISCVTargetLowering TLInfo;
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/// Initializes using the passed in CPU and feature strings so that we can
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/// use initializer lists for subtarget initialization.
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RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
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StringRef CPU,
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StringRef TuneCPU,
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StringRef FS,
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StringRef ABIName);
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public:
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// Initializes the data members to match that of the specified triple.
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RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
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StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin,
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unsigned RVVVectorLMULMax, const TargetMachine &TM);
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~RISCVSubtarget() override;
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// Parses features string setting specified subtarget options. The
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// definition of this function is auto-generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
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const RISCVFrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; }
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const RISCVRegisterInfo *getRegisterInfo() const override {
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return &RegInfo;
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}
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const RISCVTargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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bool enableMachineScheduler() const override { return true; }
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bool enablePostRAScheduler() const override { return UsePostRAScheduler; }
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Align getPrefFunctionAlignment() const {
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return Align(TuneInfo->PrefFunctionAlignment);
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}
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Align getPrefLoopAlignment() const {
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return Align(TuneInfo->PrefLoopAlignment);
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}
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/// Returns RISC-V processor family.
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/// Avoid this function! CPU specifics should be kept local to this class
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/// and preferably modeled with SubtargetFeatures or properties in
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/// initializeProperties().
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RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
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RISCVVRGatherCostModelEnum getVRGatherCostModel() const { return RISCVVRGatherCostModel; }
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#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
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bool GETTER() const { return ATTRIBUTE; }
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#include "RISCVGenSubtargetInfo.inc"
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LLVM_DEPRECATED("Now Equivalent to hasStdExtZca", "hasStdExtZca")
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bool hasStdExtCOrZca() const { return HasStdExtZca; }
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bool hasStdExtCOrZcd() const { return HasStdExtC || HasStdExtZcd; }
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bool hasStdExtCOrZcfOrZce() const {
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return HasStdExtC || HasStdExtZcf || HasStdExtZce;
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}
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bool hasStdExtZvl() const { return ZvlLen != 0; }
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bool hasStdExtFOrZfinx() const { return HasStdExtF || HasStdExtZfinx; }
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bool hasStdExtDOrZdinx() const { return HasStdExtD || HasStdExtZdinx; }
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bool hasStdExtZfhOrZhinx() const { return HasStdExtZfh || HasStdExtZhinx; }
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bool hasStdExtZfhminOrZhinxmin() const {
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return HasStdExtZfhmin || HasStdExtZhinxmin;
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}
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bool hasHalfFPLoadStoreMove() const {
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return HasStdExtZfhmin || HasStdExtZfbfmin;
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}
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bool hasConditionalMoveFusion() const {
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// Do we support fusing a branch+mv or branch+c.mv as a conditional move.
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return (hasConditionalCompressedMoveFusion() && hasStdExtZca()) ||
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hasShortForwardBranchOpt();
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}
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bool is64Bit() const { return IsRV64; }
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MVT getXLenVT() const {
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return is64Bit() ? MVT::i64 : MVT::i32;
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}
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unsigned getXLen() const {
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return is64Bit() ? 64 : 32;
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}
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bool useLoadStorePairs() const;
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bool useCCMovInsn() const;
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unsigned getFLen() const {
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if (HasStdExtD)
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return 64;
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if (HasStdExtF)
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return 32;
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return 0;
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}
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unsigned getELen() const {
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assert(hasVInstructions() && "Expected V extension");
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return hasVInstructionsI64() ? 64 : 32;
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}
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unsigned getRealMinVLen() const {
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unsigned VLen = getMinRVVVectorSizeInBits();
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return VLen == 0 ? ZvlLen : VLen;
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}
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unsigned getRealMaxVLen() const {
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unsigned VLen = getMaxRVVVectorSizeInBits();
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return VLen == 0 ? 65536 : VLen;
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}
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// If we know the exact VLEN, return it. Otherwise, return std::nullopt.
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std::optional<unsigned> getRealVLen() const {
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unsigned Min = getRealMinVLen();
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if (Min != getRealMaxVLen())
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return std::nullopt;
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return Min;
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}
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/// If the ElementCount or TypeSize \p X is scalable and VScale (VLEN) is
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/// exactly known, returns \p X converted to a fixed quantity. Otherwise
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/// returns \p X unmodified.
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template <typename Quantity> Quantity expandVScale(Quantity X) const {
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if (auto VLen = getRealVLen(); VLen && X.isScalable()) {
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const unsigned VScale = *VLen / RISCV::RVVBitsPerBlock;
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X = Quantity::getFixed(X.getKnownMinValue() * VScale);
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}
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return X;
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}
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RISCVABI::ABI getTargetABI() const { return TargetABI; }
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bool isSoftFPABI() const {
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return TargetABI == RISCVABI::ABI_LP64 ||
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TargetABI == RISCVABI::ABI_ILP32 ||
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TargetABI == RISCVABI::ABI_ILP32E;
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}
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bool isRegisterReservedByUser(Register i) const override {
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assert(i.id() < RISCV::NUM_TARGET_REGS && "Register out of range");
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return UserReservedRegister[i.id()];
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}
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// XRay support - require D and C extensions.
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bool isXRaySupported() const override { return hasStdExtD() && hasStdExtC(); }
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// Vector codegen related methods.
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bool hasVInstructions() const { return HasStdExtZve32x; }
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bool hasVInstructionsI64() const { return HasStdExtZve64x; }
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bool hasVInstructionsF16Minimal() const { return HasStdExtZvfhmin; }
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bool hasVInstructionsF16() const { return HasStdExtZvfh; }
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bool hasVInstructionsBF16Minimal() const { return HasStdExtZvfbfmin; }
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bool hasVInstructionsF32() const { return HasStdExtZve32f; }
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bool hasVInstructionsF64() const { return HasStdExtZve64d; }
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// F16 and F64 both require F32.
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bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
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bool hasVInstructionsFullMultiply() const { return HasStdExtV; }
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unsigned getMaxInterleaveFactor() const {
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return hasVInstructions() ? MaxInterleaveFactor : 1;
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}
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bool hasOptimizedSegmentLoadStore(unsigned NF) const {
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switch (NF) {
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case 2:
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return hasOptimizedNF2SegmentLoadStore();
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case 3:
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return hasOptimizedNF3SegmentLoadStore();
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case 4:
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return hasOptimizedNF4SegmentLoadStore();
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case 5:
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return hasOptimizedNF5SegmentLoadStore();
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case 6:
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return hasOptimizedNF6SegmentLoadStore();
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case 7:
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return hasOptimizedNF7SegmentLoadStore();
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case 8:
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return hasOptimizedNF8SegmentLoadStore();
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default:
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llvm_unreachable("Unexpected NF");
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}
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}
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// Returns VLEN divided by DLEN. Where DLEN is the datapath width of the
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// vector hardware implementation which may be less than VLEN.
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unsigned getDLenFactor() const {
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if (DLenFactor2)
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return 2;
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return 1;
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}
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protected:
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// SelectionDAGISel related APIs.
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std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
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// GlobalISel related APIs.
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mutable std::unique_ptr<CallLowering> CallLoweringInfo;
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mutable std::unique_ptr<InstructionSelector> InstSelector;
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mutable std::unique_ptr<LegalizerInfo> Legalizer;
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mutable std::unique_ptr<RISCVRegisterBankInfo> RegBankInfo;
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// Return the known range for the bit length of RVV data registers as set
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// at the command line. A value of 0 means nothing is known about that particular
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// limit beyond what's implied by the architecture.
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// NOTE: Please use getRealMinVLen and getRealMaxVLen instead!
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unsigned getMaxRVVVectorSizeInBits() const;
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unsigned getMinRVVVectorSizeInBits() const;
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public:
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const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
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const CallLowering *getCallLowering() const override;
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InstructionSelector *getInstructionSelector() const override;
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const LegalizerInfo *getLegalizerInfo() const override;
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const RISCVRegisterBankInfo *getRegBankInfo() const override;
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bool isTargetAndroid() const { return getTargetTriple().isAndroid(); }
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bool isTargetFuchsia() const { return getTargetTriple().isOSFuchsia(); }
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bool useConstantPoolForLargeInts() const;
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// Maximum cost used for building integers, integers will be put into constant
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// pool if exceeded.
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unsigned getMaxBuildIntsCost() const;
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unsigned getMaxLMULForFixedLengthVectors() const;
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bool useRVVForFixedLengthVectors() const;
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bool enableSubRegLiveness() const override;
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bool enableMachinePipeliner() const override;
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bool useDFAforSMS() const override { return false; }
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bool useAA() const override;
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unsigned getCacheLineSize() const override {
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return TuneInfo->CacheLineSize;
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};
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unsigned getPrefetchDistance() const override {
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return TuneInfo->PrefetchDistance;
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};
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unsigned getMinPrefetchStride(unsigned NumMemAccesses,
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unsigned NumStridedMemAccesses,
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unsigned NumPrefetches,
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bool HasCall) const override {
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return TuneInfo->MinPrefetchStride;
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};
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unsigned getMaxPrefetchIterationsAhead() const override {
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return TuneInfo->MaxPrefetchIterationsAhead;
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};
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bool enableWritePrefetching() const override { return true; }
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unsigned getMinimumJumpTableEntries() const;
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unsigned getTailDupAggressiveThreshold() const {
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return TuneInfo->TailDupAggressiveThreshold;
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}
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unsigned getMaxStoresPerMemset(bool OptSize) const {
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return OptSize ? TuneInfo->MaxStoresPerMemsetOptSize
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: TuneInfo->MaxStoresPerMemset;
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}
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unsigned getMaxGluedStoresPerMemcpy() const {
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return TuneInfo->MaxGluedStoresPerMemcpy;
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}
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unsigned getMaxStoresPerMemcpy(bool OptSize) const {
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return OptSize ? TuneInfo->MaxStoresPerMemcpyOptSize
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: TuneInfo->MaxStoresPerMemcpy;
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}
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unsigned getMaxStoresPerMemmove(bool OptSize) const {
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return OptSize ? TuneInfo->MaxStoresPerMemmoveOptSize
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: TuneInfo->MaxStoresPerMemmove;
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}
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unsigned getMaxLoadsPerMemcmp(bool OptSize) const {
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return OptSize ? TuneInfo->MaxLoadsPerMemcmpOptSize
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: TuneInfo->MaxLoadsPerMemcmp;
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}
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MISched::Direction getPostRASchedDirection() const {
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return TuneInfo->PostRASchedDirection;
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}
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void overrideSchedPolicy(MachineSchedPolicy &Policy,
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const SchedRegion &Region) const override;
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void overridePostRASchedPolicy(MachineSchedPolicy &Policy,
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const SchedRegion &Region) const override;
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};
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} // namespace llvm
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#endif
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