420 lines
16 KiB
LLVM
420 lines
16 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,MUBUF %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX9-MUBUF,MUBUF %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-promote-alloca,+enable-flat-scratch -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX9-FLATSCR %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck --check-prefixes=GFX11 %s
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; Test that non-entry function frame indices are expanded properly to
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; give an index relative to the scratch wave offset register
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; Materialize into a mov. Make sure there isn't an unnecessary copy.
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; GCN-LABEL: {{^}}func_mov_fi_i32:
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; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CI-NEXT: v_lshr_b32_e64 v0, s32, 6
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; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 v0, 6, s32
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; GFX9-FLATSCR: v_mov_b32_e32 v0, s32
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; GFX9-FLATSCR-NOT: v_lshrrev_b32_e64
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; MUBUF-NOT: v_mov
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; GCN: ds_write_b32 v0, v0
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define void @func_mov_fi_i32() #0 {
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%alloca = alloca i32, addrspace(5)
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store volatile ptr addrspace(5) %alloca, ptr addrspace(3) poison
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ret void
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}
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; Offset due to different objects
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; GCN-LABEL: {{^}}func_mov_fi_i32_offset:
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; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CI-DAG: v_lshr_b32_e64 v0, s32, 6
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; CI-NOT: v_mov
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; CI: ds_write_b32 v0, v0
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; CI-NEXT: v_lshr_b32_e64 [[SCALED:v[0-9]+]], s32, 6
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; CI-NEXT: v_add_i32_e{{32|64}} v0, {{s\[[0-9]+:[0-9]+\]|vcc}}, 4, [[SCALED]]
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; CI-NEXT: ds_write_b32 v0, v0
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; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 v0, 6, s32
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; GFX9-FLATSCR: v_mov_b32_e32 v0, s32
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; GFX9-FLATSCR: s_add_i32 [[ADD:[^,]+]], s32, 4
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; GFX9-NEXT: ds_write_b32 v0, v0
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; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
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; GFX9-MUBUF-NEXT: v_add_u32_e32 v0, 4, [[SCALED]]
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; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, [[ADD]]
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; GFX9-NEXT: ds_write_b32 v0, v0
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define void @func_mov_fi_i32_offset() #0 {
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%alloca0 = alloca i32, addrspace(5)
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%alloca1 = alloca i32, addrspace(5)
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store volatile ptr addrspace(5) %alloca0, ptr addrspace(3) poison
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store volatile ptr addrspace(5) %alloca1, ptr addrspace(3) poison
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ret void
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}
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; Materialize into an add of a constant offset from the FI.
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; FIXME: Should be able to merge adds
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; GCN-LABEL: {{^}}func_add_constant_to_fi_i32:
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; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CI: v_lshr_b32_e64 [[SCALED:v[0-9]+]], s32, 6
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; CI-NEXT: v_add_i32_e32 v0, vcc, 4, [[SCALED]]
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; GFX9-MUBUF: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
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; GFX9-MUBUF-NEXT: v_add_u32_e32 v0, 4, [[SCALED]]
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; FIXME: Should commute and shrink
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; GFX9-FLATSCR: v_add_u32_e64 v0, 4, s32
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; GCN-NOT: v_mov
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; GCN: ds_write_b32 v0, v0
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define void @func_add_constant_to_fi_i32() #0 {
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%alloca = alloca [2 x i32], align 4, addrspace(5)
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%gep0 = getelementptr inbounds [2 x i32], ptr addrspace(5) %alloca, i32 0, i32 1
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store volatile ptr addrspace(5) %gep0, ptr addrspace(3) poison
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ret void
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}
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; A user the materialized frame index can't be meaningfully folded
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; into.
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; FIXME: Should use s_mul but the frame index always gets materialized into a
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; vgpr
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; GCN-LABEL: {{^}}func_other_fi_user_i32:
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; MUBUF: s_lshr_b32 [[SCALED:s[0-9]+]], s32, 6
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; MUBUF: s_mul_i32 [[MUL:s[0-9]+]], [[SCALED]], 9
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; MUBUF: v_mov_b32_e32 v0, [[MUL]]
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; GFX9-FLATSCR: s_mul_i32 [[MUL:s[0-9]+]], s32, 9
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; GFX9-FLATSCR: v_mov_b32_e32 v0, [[MUL]]
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; GCN-NOT: v_mov
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; GCN: ds_write_b32 v0, v0
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define void @func_other_fi_user_i32() #0 {
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%alloca = alloca [2 x i32], align 4, addrspace(5)
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%ptrtoint = ptrtoint ptr addrspace(5) %alloca to i32
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%mul = mul i32 %ptrtoint, 9
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store volatile i32 %mul, ptr addrspace(3) poison
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ret void
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}
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; GCN-LABEL: {{^}}func_store_private_arg_i32_ptr:
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; GCN: v_mov_b32_e32 v1, 15{{$}}
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; MUBUF: buffer_store_dword v1, v0, s[0:3], 0 offen{{$}}
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; GFX9-FLATSCR: scratch_store_dword v0, v1, off{{$}}
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define void @func_store_private_arg_i32_ptr(ptr addrspace(5) %ptr) #0 {
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store volatile i32 15, ptr addrspace(5) %ptr
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ret void
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}
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; GCN-LABEL: {{^}}func_load_private_arg_i32_ptr:
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; GCN: s_waitcnt
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; MUBUF-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen glc{{$}}
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; GFX9-FLATSCR-NEXT: scratch_load_dword v0, v0, off glc{{$}}
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define void @func_load_private_arg_i32_ptr(ptr addrspace(5) %ptr) #0 {
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%val = load volatile i32, ptr addrspace(5) %ptr
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ret void
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}
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; GCN-LABEL: {{^}}void_func_byval_struct_i8_i32_ptr:
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; GCN: s_waitcnt
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; CI: v_lshr_b32_e64 [[SHIFT:v[0-9]+]], s32, 6
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; CI-NEXT: v_or_b32_e32 v0, 4, [[SHIFT]]
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; GFX9-MUBUF: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, s32
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; GFX9-MUBUF-NEXT: v_or_b32_e32 v0, 4, [[SHIFT]]
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; GFX9-FLATSCR: v_or_b32_e64 v0, s32, 4
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; GCN-NOT: v_mov
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; GCN: ds_write_b32 v0, v0
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define void @void_func_byval_struct_i8_i32_ptr(ptr addrspace(5) byval({ i8, i32 }) %arg0) #0 {
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%gep0 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %arg0, i32 0, i32 0
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%gep1 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %arg0, i32 0, i32 1
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%load1 = load i32, ptr addrspace(5) %gep1
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store volatile ptr addrspace(5) %gep1, ptr addrspace(3) poison
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ret void
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}
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; GCN-LABEL: {{^}}void_func_byval_struct_i8_i32_ptr_value:
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; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; MUBUF-NEXT: buffer_load_ubyte v0, off, s[0:3], s32
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; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4
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; GFX9-FLATSCR-NEXT: scratch_load_ubyte v0, off, s32
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; GFX9-FLATSCR-NEXT: scratch_load_dword v1, off, s32 offset:4
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define void @void_func_byval_struct_i8_i32_ptr_value(ptr addrspace(5) byval({ i8, i32 }) %arg0) #0 {
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%gep0 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %arg0, i32 0, i32 0
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%gep1 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %arg0, i32 0, i32 1
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%load0 = load i8, ptr addrspace(5) %gep0
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%load1 = load i32, ptr addrspace(5) %gep1
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store volatile i8 %load0, ptr addrspace(3) poison
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store volatile i32 %load1, ptr addrspace(3) poison
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ret void
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}
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; GCN-LABEL: {{^}}void_func_byval_struct_i8_i32_ptr_nonentry_block:
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; GCN: s_and_saveexec_b64
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; CI: buffer_load_dword v{{[0-9]+}}, off, s[0:3], s32 offset:4 glc{{$}}
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; GFX9-MUBUF: buffer_load_dword v{{[0-9]+}}, off, s[0:3], s32 offset:4 glc{{$}}
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; GFX9-FLATSCR: scratch_load_dword v{{[0-9]+}}, off, s32 offset:4 glc{{$}}
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; CI: v_lshr_b32_e64 [[SHIFT:v[0-9]+]], s32, 6
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; CI: v_add_i32_e64 [[GEP:v[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 4, [[SHIFT]]
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; GFX9-MUBUF: v_lshrrev_b32_e64 [[SP:v[0-9]+]], 6, s32
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; GFX9-MUBUF: v_add_u32_e32 [[GEP:v[0-9]+]], 4, [[SP]]
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; GFX9-FLATSCR: v_add_u32_e64 [[GEP:v[0-9]+]], 4, s32
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; GCN: ds_write_b32 v{{[0-9]+}}, [[GEP]]
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define void @void_func_byval_struct_i8_i32_ptr_nonentry_block(ptr addrspace(5) byval({ i8, i32 }) %arg0, i32 %arg2) #0 {
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%cmp = icmp eq i32 %arg2, 0
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br i1 %cmp, label %bb, label %ret
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bb:
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%gep0 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %arg0, i32 0, i32 0
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%gep1 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %arg0, i32 0, i32 1
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%load1 = load volatile i32, ptr addrspace(5) %gep1
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store volatile ptr addrspace(5) %gep1, ptr addrspace(3) poison
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br label %ret
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ret:
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ret void
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}
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; Added offset can't be used with VOP3 add
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; GCN-LABEL: {{^}}func_other_fi_user_non_inline_imm_offset_i32:
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; MUBUF: s_lshr_b32 [[SCALED:s[0-9]+]], s32, 6
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; MUBUF: s_addk_i32 [[SCALED]], 0x200
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; MUBUF: s_mul_i32 [[Z:s[0-9]+]], [[SCALED]], 9
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; MUBUF: v_mov_b32_e32 [[VZ:v[0-9]+]], [[Z]]
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; GFX9-FLATSCR: s_add_i32 [[SZ:[^,]+]], s32, 0x200
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; GFX9-FLATSCR: s_mul_i32 [[MUL:s[0-9]+]], [[SZ]], 9
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; GFX9-FLATSCR: v_mov_b32_e32 [[VZ:v[0-9]+]], [[MUL]]
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; GCN: ds_write_b32 v0, [[VZ]]
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define void @func_other_fi_user_non_inline_imm_offset_i32() #0 {
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%alloca0 = alloca [128 x i32], align 4, addrspace(5)
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%alloca1 = alloca [8 x i32], align 4, addrspace(5)
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%gep0 = getelementptr inbounds [128 x i32], ptr addrspace(5) %alloca0, i32 0, i32 65
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store volatile i32 7, ptr addrspace(5) %gep0
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%ptrtoint = ptrtoint ptr addrspace(5) %alloca1 to i32
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%mul = mul i32 %ptrtoint, 9
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store volatile i32 %mul, ptr addrspace(3) poison
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ret void
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}
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; GCN-LABEL: {{^}}func_other_fi_user_non_inline_imm_offset_i32_vcc_live:
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; MUBUF: s_lshr_b32 [[SCALED:s[0-9]+]], s32, 6
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; MUBUF: s_addk_i32 [[SCALED]], 0x200
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; MUBUF: s_mul_i32 [[Z:s[0-9]+]], [[SCALED]], 9
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; MUBUF: v_mov_b32_e32 [[VZ:v[0-9]+]], [[Z]]
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; GFX9-FLATSCR: s_add_i32 [[SZ:[^,]+]], s32, 0x200
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; GFX9-FLATSCR: s_mul_i32 [[MUL:s[0-9]+]], [[SZ]], 9
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; GFX9-FLATSCR: v_mov_b32_e32 [[VZ:v[0-9]+]], [[MUL]]
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; GCN: ds_write_b32 v0, [[VZ]]
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define void @func_other_fi_user_non_inline_imm_offset_i32_vcc_live() #0 {
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%alloca0 = alloca [128 x i32], align 4, addrspace(5)
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%alloca1 = alloca [8 x i32], align 4, addrspace(5)
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%vcc = call i64 asm sideeffect "; def $0", "={vcc}"()
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%gep0 = getelementptr inbounds [128 x i32], ptr addrspace(5) %alloca0, i32 0, i32 65
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store volatile i32 7, ptr addrspace(5) %gep0
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call void asm sideeffect "; use $0", "{vcc}"(i64 %vcc)
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%ptrtoint = ptrtoint ptr addrspace(5) %alloca1 to i32
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%mul = mul i32 %ptrtoint, 9
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store volatile i32 %mul, ptr addrspace(3) poison
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ret void
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}
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declare void @func(ptr addrspace(5) nocapture) #0
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; undef flag not preserved in eliminateFrameIndex when handling the
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; stores in the middle block.
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; GCN-LABEL: {{^}}undefined_stack_store_reg:
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; GCN: s_and_saveexec_b64
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; MUBUF: buffer_store_dword v0, off, s[0:3], s33 offset:
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; MUBUF: buffer_store_dword v0, off, s[0:3], s33 offset:
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; MUBUF: buffer_store_dword v0, off, s[0:3], s33 offset:
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; MUBUF: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s33 offset:
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; FLATSCR: scratch_store_dword v0, off, s33 offset:
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; FLATSCR: scratch_store_dword v0, off, s33 offset:
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; FLATSCR: scratch_store_dword v0, off, s33 offset:
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; FLATSCR: scratch_store_dword v{{[0-9]+}}, off, s33 offset:
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define void @undefined_stack_store_reg(float %arg, i32 %arg1) #0 {
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bb:
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%tmp = alloca <4 x float>, align 16, addrspace(5)
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%tmp2 = insertelement <4 x float> poison, float %arg, i32 0
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store <4 x float> %tmp2, ptr addrspace(5) poison
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%tmp3 = icmp eq i32 %arg1, 0
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br i1 %tmp3, label %bb4, label %bb5
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bb4:
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call void @func(ptr addrspace(5) nonnull undef)
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store <4 x float> %tmp2, ptr addrspace(5) %tmp, align 16
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call void @func(ptr addrspace(5) nonnull %tmp)
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br label %bb5
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bb5:
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ret void
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}
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; GCN-LABEL: {{^}}alloca_ptr_nonentry_block:
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; GCN: s_and_saveexec_b64
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; MUBUF: buffer_load_dword v{{[0-9]+}}, off, s[0:3], s32 offset:4
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; FLATSCR: scratch_load_dword v{{[0-9]+}}, off, s32 offset:4
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; CI: v_lshr_b32_e64 [[SHIFT:v[0-9]+]], s32, 6
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; CI-NEXT: v_or_b32_e32 [[PTR:v[0-9]+]], 4, [[SHIFT]]
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; GFX9-MUBUF: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, s32
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; GFX9-MUBUF-NEXT: v_or_b32_e32 [[PTR:v[0-9]+]], 4, [[SHIFT]]
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; GFX9-FLATSCR: v_or_b32_e64 [[PTR:v[0-9]+]], s32, 4
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; GCN: ds_write_b32 v{{[0-9]+}}, [[PTR]]
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define void @alloca_ptr_nonentry_block(i32 %arg0) #0 {
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%alloca0 = alloca { i8, i32 }, align 8, addrspace(5)
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%cmp = icmp eq i32 %arg0, 0
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br i1 %cmp, label %bb, label %ret
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bb:
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%gep0 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %alloca0, i32 0, i32 0
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%gep1 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %alloca0, i32 0, i32 1
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%load1 = load volatile i32, ptr addrspace(5) %gep1
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store volatile ptr addrspace(5) %gep1, ptr addrspace(3) poison
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br label %ret
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ret:
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ret void
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}
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%struct0 = type { [4224 x %type.i16] }
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%type.i16 = type { i16 }
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@_ZZN0 = external hidden addrspace(3) global %struct0, align 8
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; GFX11-LABEL: tied_operand_test:
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; GFX11: ; %bb.0: ; %entry
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; GFX11: scratch_load_u16 [[LDRESULT:v[0-9]+]], off, off
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; GFX11: v_dual_mov_b32 [[C:v[0-9]+]], 0x7b :: v_dual_mov_b32 v{{[0-9]+}}, s{{[0-9]+}}
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; GFX11-DAG: ds_store_b16 v{{[0-9]+}}, [[LDRESULT]] offset:10
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; GFX11-DAG: ds_store_b16 v{{[0-9]+}}, [[C]] offset:8
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; GFX11-NEXT: s_endpgm
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define protected amdgpu_kernel void @tied_operand_test(i1 %c1, i1 %c2, i32 %val) {
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entry:
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%scratch0 = alloca i16, align 4, addrspace(5)
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%scratch1 = alloca i16, align 4, addrspace(5)
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%first = select i1 %c1, ptr addrspace(5) %scratch0, ptr addrspace(5) %scratch1
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%spec.select = select i1 %c2, ptr addrspace(5) %first, ptr addrspace(5) %scratch0
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%dead.load = load i16, ptr addrspace(5) %spec.select, align 2
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%scratch0.load = load i16, ptr addrspace(5) %scratch0, align 4
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%add4 = add nuw nsw i32 %val, 4
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%addr0 = getelementptr inbounds %struct0, ptr addrspace(3) @_ZZN0, i32 0, i32 0, i32 %add4, i32 0
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store i16 123, ptr addrspace(3) %addr0, align 2
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%add5 = add nuw nsw i32 %val, 5
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%addr1 = getelementptr inbounds %struct0, ptr addrspace(3) @_ZZN0, i32 0, i32 0, i32 %add5, i32 0
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store i16 %scratch0.load, ptr addrspace(3) %addr1, align 2
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ret void
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}
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; GCN-LABEL: {{^}}fi_vop3_literal_error:
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; CI: v_lshr_b32_e64 [[SCALED_FP:v[0-9]+]], s33, 6
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; CI: s_movk_i32 vcc_lo, 0x3000
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; CI-NEXT: v_add_i32_e32 [[SCALED_FP]], vcc, vcc_lo, [[SCALED_FP]]
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; CI-NEXT: v_add_i32_e32 v0, vcc, 64, [[SCALED_FP]]
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; GFX9-MUBUF: v_lshrrev_b32_e64 [[SCALED_FP:v[0-9]+]], 6, s33
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; GFX9-MUBUF-NEXT: v_add_u32_e32 [[SCALED_FP]], 0x3000, [[SCALED_FP]]
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; GFX9-MUBUF-NEXT: v_add_u32_e32 v0, 64, [[SCALED_FP]]
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define void @fi_vop3_literal_error() {
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entry:
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%pin.low = alloca i32, align 8192, addrspace(5)
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%local.area = alloca [1060 x i64], align 4096, addrspace(5)
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store i32 0, ptr addrspace(5) %pin.low, align 4
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%gep.small.offset = getelementptr i8, ptr addrspace(5) %local.area, i64 64
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%load1 = load volatile i64, ptr addrspace(5) %gep.small.offset, align 4
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ret void
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|
}
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; Check for "SOP2/SOPC instruction requires too many immediate
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; constants" verifier error. Frame index would fold into low half of
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; the lowered flat pointer add, and use s_add_u32 instead of
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; s_add_i32.
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; GCN-LABEL: {{^}}fi_sop2_s_add_u32_literal_error:
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; GCN: s_add_u32 [[ADD_LO:s[0-9]+]], 0, 0x2010
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; GCN: s_addc_u32 [[ADD_HI:s[0-9]+]], s{{[0-9]+}}, 0
|
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define amdgpu_kernel void @fi_sop2_s_add_u32_literal_error() #0 {
|
|
entry:
|
|
%.omp.reduction.element.i.i.i.i = alloca [1024 x i32], align 4, addrspace(5)
|
|
%Total3.i.i = alloca [1024 x i32], align 16, addrspace(5)
|
|
%Total3.ascast.i.i = addrspacecast ptr addrspace(5) %Total3.i.i to ptr
|
|
%gep = getelementptr i8, ptr %Total3.ascast.i.i, i64 4096
|
|
%p2i = ptrtoint ptr %gep to i64
|
|
br label %.shuffle.then.i.i.i.i
|
|
|
|
.shuffle.then.i.i.i.i: ; preds = %.shuffle.then.i.i.i.i, %entry
|
|
store i64 0, ptr addrspace(5) null, align 4
|
|
%icmp = icmp ugt i64 %p2i, 1
|
|
br i1 %icmp, label %.shuffle.then.i.i.i.i, label %vector.body.i.i.i.i
|
|
|
|
vector.body.i.i.i.i: ; preds = %.shuffle.then.i.i.i.i
|
|
%wide.load9.i.i.i.i = load <2 x i32>, ptr addrspace(5) %.omp.reduction.element.i.i.i.i, align 4
|
|
store <2 x i32> %wide.load9.i.i.i.i, ptr addrspace(5) null, align 4
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}fi_sop2_and_literal_error:
|
|
; GCN: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x1fe00
|
|
define amdgpu_kernel void @fi_sop2_and_literal_error() #0 {
|
|
entry:
|
|
%.omp.reduction.element.i.i.i.i = alloca [1024 x i32], align 4, addrspace(5)
|
|
%Total3.i.i = alloca [1024 x i32], align 16, addrspace(5)
|
|
%p2i = ptrtoint ptr addrspace(5) %Total3.i.i to i32
|
|
br label %.shuffle.then.i.i.i.i
|
|
|
|
.shuffle.then.i.i.i.i: ; preds = %.shuffle.then.i.i.i.i, %entry
|
|
store i64 0, ptr addrspace(5) null, align 4
|
|
%or = and i32 %p2i, -512
|
|
%icmp = icmp ugt i32 %or, 9999999
|
|
br i1 %icmp, label %.shuffle.then.i.i.i.i, label %vector.body.i.i.i.i
|
|
|
|
vector.body.i.i.i.i: ; preds = %.shuffle.then.i.i.i.i
|
|
%wide.load9.i.i.i.i = load <2 x i32>, ptr addrspace(5) %.omp.reduction.element.i.i.i.i, align 4
|
|
store <2 x i32> %wide.load9.i.i.i.i, ptr addrspace(5) null, align 4
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}fi_sop2_or_literal_error:
|
|
; GCN: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x3039
|
|
define amdgpu_kernel void @fi_sop2_or_literal_error() #0 {
|
|
entry:
|
|
%.omp.reduction.element.i.i.i.i = alloca [1024 x i32], align 4, addrspace(5)
|
|
%Total3.i.i = alloca [1024 x i32], align 16, addrspace(5)
|
|
%p2i = ptrtoint ptr addrspace(5) %Total3.i.i to i32
|
|
br label %.shuffle.then.i.i.i.i
|
|
|
|
.shuffle.then.i.i.i.i: ; preds = %.shuffle.then.i.i.i.i, %entry
|
|
store i64 0, ptr addrspace(5) null, align 4
|
|
%or = or i32 %p2i, 12345
|
|
%icmp = icmp ugt i32 %or, 9999999
|
|
br i1 %icmp, label %.shuffle.then.i.i.i.i, label %vector.body.i.i.i.i
|
|
|
|
vector.body.i.i.i.i: ; preds = %.shuffle.then.i.i.i.i
|
|
%wide.load9.i.i.i.i = load <2 x i32>, ptr addrspace(5) %.omp.reduction.element.i.i.i.i, align 4
|
|
store <2 x i32> %wide.load9.i.i.i.i, ptr addrspace(5) null, align 4
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { nounwind }
|