0d88f662ff
We're missing SimplifyDemandedBits styles of optimizations, so one case differs from the DAG from not trimming the constant. The other case is an optimization we get that the DAG doesn't do to split the 64-bit shift. https://reviews.llvm.org/D138082
168 lines
6.3 KiB
LLVM
168 lines
6.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SDAG %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GISEL %s
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define i32 @range_metadata_sext_i8_signed_range_i32(ptr addrspace(1) %ptr) {
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; GCN-LABEL: range_metadata_sext_i8_signed_range_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: global_load_dword v0, v[0:1], off glc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%val = load volatile i32, ptr addrspace(1) %ptr, align 4, !range !0, !noundef !{} ; [-127, 128)
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%shl = shl i32 %val, 24
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%ashr = ashr i32 %shl, 24
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ret i32 %ashr
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}
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define i32 @range_metadata_sext_upper_range_limited_i32(ptr addrspace(1) %ptr) {
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; GCN-LABEL: range_metadata_sext_upper_range_limited_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: global_load_dword v0, v[0:1], off glc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_bfe_i32 v0, v0, 0, 8
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%val = load volatile i32, ptr addrspace(1) %ptr, align 4, !range !1, !noundef !{} ; [-127, 256)
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%shl = shl i32 %val, 24
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%ashr = ashr i32 %shl, 24
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ret i32 %ashr
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}
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define i32 @range_metadata_sext_lower_range_limited_i32(ptr addrspace(1) %ptr) {
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; GCN-LABEL: range_metadata_sext_lower_range_limited_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: global_load_dword v0, v[0:1], off glc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_bfe_i32 v0, v0, 0, 8
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%val = load volatile i32, ptr addrspace(1) %ptr, align 4, !range !2 ; [-255, 128)
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%shl = shl i32 %val, 24
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%ashr = ashr i32 %shl, 24
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ret i32 %ashr
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}
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define i32 @range_metadata_sext_i8_neg_neg_range_i32(ptr addrspace(1) %ptr) {
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; SDAG-LABEL: range_metadata_sext_i8_neg_neg_range_i32:
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; SDAG: ; %bb.0:
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: global_load_dword v0, v[0:1], off glc
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; SDAG-NEXT: s_waitcnt vmcnt(0)
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; SDAG-NEXT: v_and_b32_e32 v0, 63, v0
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; SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GISEL-LABEL: range_metadata_sext_i8_neg_neg_range_i32:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: global_load_dword v0, v[0:1], off glc
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; GISEL-NEXT: s_waitcnt vmcnt(0)
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; GISEL-NEXT: v_and_b32_e32 v0, 0x7f, v0
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; GISEL-NEXT: s_setpc_b64 s[30:31]
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%val = load volatile i32, ptr addrspace(1) %ptr, align 4, !range !3, !noundef !{}
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%shl = shl i32 %val, 25
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%ashr = ashr i32 %shl, 25
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ret i32 %ashr
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}
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define i32 @range_metadata_sextload_i8_signed_range_i4_i32(ptr addrspace(1) %ptr) {
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; GCN-LABEL: range_metadata_sextload_i8_signed_range_i4_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: global_load_sbyte v0, v[0:1], off glc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%load = load volatile i8, ptr addrspace(1) %ptr, align 1, !range !4, !noundef !{}
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%shl = shl i8 %load, 3
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%ashr = ashr i8 %shl, 3
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%ext = sext i8 %ashr to i32
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ret i32 %ext
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}
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define i25 @range_metadata_sext_i8_signed_range_i25(ptr addrspace(1) %ptr) {
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; GCN-LABEL: range_metadata_sext_i8_signed_range_i25:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: global_load_dword v0, v[0:1], off glc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_bfe_i32 v0, v0, 0, 2
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%val = load volatile i25, ptr addrspace(1) %ptr, align 4, !range !5, !noundef !{}
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%shl = shl i25 %val, 23
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%ashr = ashr i25 %shl, 23
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ret i25 %ashr
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}
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define i32 @range_metadata_i32_neg1_to_1(ptr addrspace(1) %ptr) {
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; GCN-LABEL: range_metadata_i32_neg1_to_1:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: global_load_dword v0, v[0:1], off glc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%val = load volatile i32, ptr addrspace(1) %ptr, align 4, !range !6, !noundef !{}
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%shl = shl i32 %val, 31
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%ashr = ashr i32 %shl, 31
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ret i32 %ashr
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}
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define i64 @range_metadata_sext_i8_signed_range_i64(ptr addrspace(1) %ptr) {
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; SDAG-LABEL: range_metadata_sext_i8_signed_range_i64:
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; SDAG: ; %bb.0:
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: global_load_dwordx2 v[0:1], v[0:1], off glc
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; SDAG-NEXT: s_waitcnt vmcnt(0)
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; SDAG-NEXT: v_lshlrev_b32_e32 v1, 23, v0
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; SDAG-NEXT: v_ashrrev_i64 v[0:1], 55, v[0:1]
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; SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GISEL-LABEL: range_metadata_sext_i8_signed_range_i64:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: global_load_dwordx2 v[0:1], v[0:1], off glc
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; GISEL-NEXT: s_waitcnt vmcnt(0)
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; GISEL-NEXT: v_bfe_i32 v0, v0, 0, 9
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; GISEL-NEXT: v_ashrrev_i32_e32 v1, 31, v0
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; GISEL-NEXT: s_setpc_b64 s[30:31]
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%val = load volatile i64, ptr addrspace(1) %ptr, align 4, !range !7, !noundef !{}
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%shl = shl i64 %val, 55
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%ashr = ashr i64 %shl, 55
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ret i64 %ashr
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}
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define i64 @range_metadata_sext_i32_signed_range_i64(ptr addrspace(1) %ptr) {
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; GCN-LABEL: range_metadata_sext_i32_signed_range_i64:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: global_load_dwordx2 v[0:1], v[0:1], off glc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%val = load volatile i64, ptr addrspace(1) %ptr, align 4, !range !7, !noundef !{}
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%shl = shl i64 %val, 31
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%ashr = ashr i64 %shl, 31
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ret i64 %ashr
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}
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define i64 @range_metadata_sext_i33_signed_range_i64(ptr addrspace(1) %ptr) {
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; GCN-LABEL: range_metadata_sext_i33_signed_range_i64:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: global_load_dwordx2 v[0:1], v[0:1], off glc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%val = load volatile i64, ptr addrspace(1) %ptr, align 4, !range !8, !noundef !{}
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%shl = shl i64 %val, 30
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%ashr = ashr i64 %shl, 30
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ret i64 %ashr
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}
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!0 = !{i32 -127, i32 128}
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!1 = !{i32 -127, i32 256}
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!2 = !{i32 -255, i32 128}
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!3 = !{i32 -127, i32 -64}
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!4 = !{i8 -15, i8 16}
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!5 = !{i25 -127, i25 128}
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!6 = !{i32 -1, i32 1}
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!7 = !{i64 -4294967295, i64 4294967296}
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!8 = !{i64 -8589934591, i64 8589934592}
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