9d7e1d92db
The allocation order of 16 bit registers is vgpr0lo16, vgpr0hi16, vgpr1lo16, vgpr1hi16, vgpr2lo16.... We prefer (essentially require) that allocation order, because it uses the minimum number of registers. But when you have 16 bit data passing between 16 and 32 bit instructions you get lots of COPY. This patch teach the compiler that a COPY of a 16-bit value from a 32 bit register to a lo-half 16 bit register is free, to a hi-half 16 bit register is not. This might get improved to coalescing with additional cases, and perhaps as an alternative to the RA hints. For now upstreaming this solution first.
924 lines
39 KiB
LLVM
924 lines
39 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,SDAG,SDAG-GFX11,SDAG-GFX11-TRUE16 %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,SDAG,SDAG-GFX11,SDAG-GFX11-FAKE16 %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GISEL,GISEL-GFX11,GISEL-GFX11-TRUE16 %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GISEL,GISEL-GFX11,GISEL-GFX11-FAKE16 %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,SDAG,SDAG-GFX12,SDAG-GFX12-TRUE16 %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,SDAG,SDAG-GFX12,SDAG-GFX12-FAKE16 %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GISEL,GISEL-GFX12,GISEL-GFX12-TRUE16 %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GISEL,GISEL-GFX12,GISEL-GFX12-FAKE16 %s
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define i32 @test_minmax_i32(i32 %a, i32 %b, i32 %c) {
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; GFX11-LABEL: test_minmax_i32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_maxmin_i32 v0, v0, v1, v2
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: test_minmax_i32:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_maxmin_i32 v0, v0, v1, v2
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%smax = call i32 @llvm.smax.i32(i32 %a, i32 %b)
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%sminmax = call i32 @llvm.smin.i32(i32 %smax, i32 %c)
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ret i32 %sminmax
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}
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define amdgpu_ps void @s_test_minmax_i32(i32 inreg %a, i32 inreg %b, i32 inreg %c, ptr addrspace(1) inreg %out) {
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; SDAG-LABEL: s_test_minmax_i32:
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; SDAG: ; %bb.0:
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; SDAG-NEXT: s_max_i32 s0, s0, s1
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; SDAG-NEXT: s_mov_b32 s5, s4
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; SDAG-NEXT: s_min_i32 s0, s0, s2
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; SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
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; SDAG-NEXT: s_mov_b32 s4, s3
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; SDAG-NEXT: global_store_b32 v0, v1, s[4:5]
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; SDAG-NEXT: s_endpgm
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;
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; GISEL-LABEL: s_test_minmax_i32:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_max_i32 s0, s0, s1
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; GISEL-NEXT: s_mov_b32 s6, s3
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; GISEL-NEXT: s_min_i32 s0, s0, s2
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; GISEL-NEXT: s_mov_b32 s7, s4
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; GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, 0
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; GISEL-NEXT: global_store_b32 v1, v0, s[6:7]
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; GISEL-NEXT: s_endpgm
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%smax = call i32 @llvm.smax.i32(i32 %a, i32 %b)
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%sminmax = call i32 @llvm.smin.i32(i32 %smax, i32 %c)
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store i32 %sminmax, ptr addrspace(1) %out
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ret void
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}
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define i32 @test_minmax_commuted_i32(i32 %a, i32 %b, i32 %c) {
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; GFX11-LABEL: test_minmax_commuted_i32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_maxmin_i32 v0, v0, v1, v2
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: test_minmax_commuted_i32:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_maxmin_i32 v0, v0, v1, v2
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%smax = call i32 @llvm.smax.i32(i32 %a, i32 %b)
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%sminmax = call i32 @llvm.smin.i32(i32 %c, i32 %smax)
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ret i32 %sminmax
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}
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define i32 @test_maxmin_i32(i32 %a, i32 %b, i32 %c) {
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; GFX11-LABEL: test_maxmin_i32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_minmax_i32 v0, v0, v1, v2
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: test_maxmin_i32:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_minmax_i32 v0, v0, v1, v2
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%smin = call i32 @llvm.smin.i32(i32 %a, i32 %b)
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%smaxmin = call i32 @llvm.smax.i32(i32 %smin, i32 %c)
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ret i32 %smaxmin
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}
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define i32 @test_maxmin_commuted_i32(i32 %a, i32 %b, i32 %c) {
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; GFX11-LABEL: test_maxmin_commuted_i32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_minmax_i32 v0, v0, v1, v2
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: test_maxmin_commuted_i32:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_minmax_i32 v0, v0, v1, v2
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%smin = call i32 @llvm.smin.i32(i32 %a, i32 %b)
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%smaxmin = call i32 @llvm.smax.i32(i32 %c, i32 %smin)
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ret i32 %smaxmin
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}
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define void @test_smed3_i32(ptr addrspace(1) %arg, i32 %x, i32 %y, i32 %z) {
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; GFX11-LABEL: test_smed3_i32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_med3_i32 v2, v2, v3, v4
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; GFX11-NEXT: global_store_b32 v[0:1], v2, off
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: test_smed3_i32:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_med3_i32 v2, v2, v3, v4
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; GFX12-NEXT: global_store_b32 v[0:1], v2, off
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%tmp0 = call i32 @llvm.smin.i32(i32 %x, i32 %y)
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%tmp1 = call i32 @llvm.smax.i32(i32 %x, i32 %y)
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%tmp2 = call i32 @llvm.smin.i32(i32 %tmp1, i32 %z)
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%tmp3 = call i32 @llvm.smax.i32(i32 %tmp0, i32 %tmp2)
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store i32 %tmp3, ptr addrspace(1) %arg
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ret void
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}
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define i32 @test_minmax_u32(i32 %a, i32 %b, i32 %c) {
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; GFX11-LABEL: test_minmax_u32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_maxmin_u32 v0, v0, v1, v2
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: test_minmax_u32:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_maxmin_u32 v0, v0, v1, v2
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%umax = call i32 @llvm.umax.i32(i32 %a, i32 %b)
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%uminmax = call i32 @llvm.umin.i32(i32 %umax, i32 %c)
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ret i32 %uminmax
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}
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define amdgpu_ps void @s_test_minmax_u32(i32 inreg %a, i32 inreg %b, i32 inreg %c, ptr addrspace(1) inreg %out) {
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; SDAG-LABEL: s_test_minmax_u32:
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; SDAG: ; %bb.0:
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; SDAG-NEXT: s_max_u32 s0, s0, s1
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; SDAG-NEXT: s_mov_b32 s5, s4
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; SDAG-NEXT: s_min_u32 s0, s0, s2
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; SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
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; SDAG-NEXT: s_mov_b32 s4, s3
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; SDAG-NEXT: global_store_b32 v0, v1, s[4:5]
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; SDAG-NEXT: s_endpgm
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;
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; GISEL-LABEL: s_test_minmax_u32:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_max_u32 s0, s0, s1
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; GISEL-NEXT: s_mov_b32 s6, s3
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; GISEL-NEXT: s_min_u32 s0, s0, s2
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; GISEL-NEXT: s_mov_b32 s7, s4
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; GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, 0
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; GISEL-NEXT: global_store_b32 v1, v0, s[6:7]
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; GISEL-NEXT: s_endpgm
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%smax = call i32 @llvm.umax.i32(i32 %a, i32 %b)
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%sminmax = call i32 @llvm.umin.i32(i32 %smax, i32 %c)
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store i32 %sminmax, ptr addrspace(1) %out
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ret void
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}
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define i32 @test_minmax_commuted_u32(i32 %a, i32 %b, i32 %c) {
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; GFX11-LABEL: test_minmax_commuted_u32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_maxmin_u32 v0, v0, v1, v2
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: test_minmax_commuted_u32:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_maxmin_u32 v0, v0, v1, v2
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%umax = call i32 @llvm.umax.i32(i32 %a, i32 %b)
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%uminmax = call i32 @llvm.umin.i32(i32 %c, i32 %umax)
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ret i32 %uminmax
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}
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define i32 @test_maxmin_u32(i32 %a, i32 %b, i32 %c) {
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; GFX11-LABEL: test_maxmin_u32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_minmax_u32 v0, v0, v1, v2
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: test_maxmin_u32:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_minmax_u32 v0, v0, v1, v2
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%umin = call i32 @llvm.umin.i32(i32 %a, i32 %b)
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%umaxmin = call i32 @llvm.umax.i32(i32 %umin, i32 %c)
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ret i32 %umaxmin
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}
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define i32 @test_maxmin_commuted_u32(i32 %a, i32 %b, i32 %c) {
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; GFX11-LABEL: test_maxmin_commuted_u32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_minmax_u32 v0, v0, v1, v2
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: test_maxmin_commuted_u32:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_minmax_u32 v0, v0, v1, v2
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%umin = call i32 @llvm.umin.i32(i32 %a, i32 %b)
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%umaxmin = call i32 @llvm.umax.i32(i32 %c, i32 %umin)
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ret i32 %umaxmin
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}
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define void @test_umed3_i32(ptr addrspace(1) %arg, i32 %x, i32 %y, i32 %z) {
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; GFX11-LABEL: test_umed3_i32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_med3_u32 v2, v2, v3, v4
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; GFX11-NEXT: global_store_b32 v[0:1], v2, off
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: test_umed3_i32:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: v_med3_u32 v2, v2, v3, v4
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; GFX12-NEXT: global_store_b32 v[0:1], v2, off
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%tmp0 = call i32 @llvm.umin.i32(i32 %x, i32 %y)
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%tmp1 = call i32 @llvm.umax.i32(i32 %x, i32 %y)
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%tmp2 = call i32 @llvm.umin.i32(i32 %tmp1, i32 %z)
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%tmp3 = call i32 @llvm.umax.i32(i32 %tmp0, i32 %tmp2)
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store i32 %tmp3, ptr addrspace(1) %arg
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ret void
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}
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define float @test_minmax_f32_ieee_true(float %a, float %b, float %c) {
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; SDAG-GFX11-LABEL: test_minmax_f32_ieee_true:
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; SDAG-GFX11: ; %bb.0:
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; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-GFX11-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0
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; SDAG-GFX11-NEXT: v_max_f32_e32 v2, v2, v2
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; SDAG-GFX11-NEXT: v_maxmin_f32 v0, v0, v1, v2
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; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31]
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;
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; GISEL-GFX11-LABEL: test_minmax_f32_ieee_true:
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; GISEL-GFX11: ; %bb.0:
|
|
; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GISEL-GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
|
|
; GISEL-GFX11-NEXT: v_max_f32_e32 v2, v2, v2
|
|
; GISEL-GFX11-NEXT: v_maxmin_f32 v0, v0, v1, v2
|
|
; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; SDAG-GFX12-LABEL: test_minmax_f32_ieee_true:
|
|
; SDAG-GFX12: ; %bb.0:
|
|
; SDAG-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
|
|
; SDAG-GFX12-NEXT: s_wait_expcnt 0x0
|
|
; SDAG-GFX12-NEXT: s_wait_samplecnt 0x0
|
|
; SDAG-GFX12-NEXT: s_wait_bvhcnt 0x0
|
|
; SDAG-GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; SDAG-GFX12-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
|
|
; SDAG-GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2
|
|
; SDAG-GFX12-NEXT: v_maxmin_num_f32 v0, v0, v1, v2
|
|
; SDAG-GFX12-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GISEL-GFX12-LABEL: test_minmax_f32_ieee_true:
|
|
; GISEL-GFX12: ; %bb.0:
|
|
; GISEL-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
|
|
; GISEL-GFX12-NEXT: s_wait_expcnt 0x0
|
|
; GISEL-GFX12-NEXT: s_wait_samplecnt 0x0
|
|
; GISEL-GFX12-NEXT: s_wait_bvhcnt 0x0
|
|
; GISEL-GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GISEL-GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
|
|
; GISEL-GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2
|
|
; GISEL-GFX12-NEXT: v_maxmin_num_f32 v0, v0, v1, v2
|
|
; GISEL-GFX12-NEXT: s_setpc_b64 s[30:31]
|
|
%max = call float @llvm.maxnum.f32(float %a, float %b)
|
|
%minmax = call float @llvm.minnum.f32(float %max, float %c)
|
|
ret float %minmax
|
|
}
|
|
|
|
define amdgpu_ps void @s_test_minmax_f32_ieee_false(float inreg %a, float inreg %b, float inreg %c, ptr addrspace(1) inreg %out) {
|
|
; SDAG-GFX11-LABEL: s_test_minmax_f32_ieee_false:
|
|
; SDAG-GFX11: ; %bb.0:
|
|
; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
|
|
; SDAG-GFX11-NEXT: s_mov_b32 s5, s4
|
|
; SDAG-GFX11-NEXT: s_mov_b32 s4, s3
|
|
; SDAG-GFX11-NEXT: v_maxmin_f32 v0, s0, s1, v0
|
|
; SDAG-GFX11-NEXT: global_store_b32 v1, v0, s[4:5]
|
|
; SDAG-GFX11-NEXT: s_endpgm
|
|
;
|
|
; GISEL-GFX11-LABEL: s_test_minmax_f32_ieee_false:
|
|
; GISEL-GFX11: ; %bb.0:
|
|
; GISEL-GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
|
|
; GISEL-GFX11-NEXT: s_mov_b32 s6, s3
|
|
; GISEL-GFX11-NEXT: s_mov_b32 s7, s4
|
|
; GISEL-GFX11-NEXT: v_maxmin_f32 v0, s0, s1, v0
|
|
; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[6:7]
|
|
; GISEL-GFX11-NEXT: s_endpgm
|
|
;
|
|
; SDAG-GFX12-LABEL: s_test_minmax_f32_ieee_false:
|
|
; SDAG-GFX12: ; %bb.0:
|
|
; SDAG-GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
|
|
; SDAG-GFX12-NEXT: s_mov_b32 s5, s4
|
|
; SDAG-GFX12-NEXT: s_mov_b32 s4, s3
|
|
; SDAG-GFX12-NEXT: v_maxmin_num_f32 v0, s0, s1, v0
|
|
; SDAG-GFX12-NEXT: global_store_b32 v1, v0, s[4:5]
|
|
; SDAG-GFX12-NEXT: s_endpgm
|
|
;
|
|
; GISEL-GFX12-LABEL: s_test_minmax_f32_ieee_false:
|
|
; GISEL-GFX12: ; %bb.0:
|
|
; GISEL-GFX12-NEXT: s_max_num_f32 s0, s0, s1
|
|
; GISEL-GFX12-NEXT: s_mov_b32 s6, s3
|
|
; GISEL-GFX12-NEXT: s_mov_b32 s7, s4
|
|
; GISEL-GFX12-NEXT: v_mov_b32_e32 v1, 0
|
|
; GISEL-GFX12-NEXT: s_min_num_f32 s0, s0, s2
|
|
; GISEL-GFX12-NEXT: v_mov_b32_e32 v0, s0
|
|
; GISEL-GFX12-NEXT: global_store_b32 v1, v0, s[6:7]
|
|
; GISEL-GFX12-NEXT: s_endpgm
|
|
%smax = call float @llvm.maxnum.f32(float %a, float %b)
|
|
%sminmax = call float @llvm.minnum.f32(float %smax, float %c)
|
|
store float %sminmax, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps float @test_minmax_commuted_f32_ieee_false(float %a, float %b, float %c) {
|
|
; GFX11-LABEL: test_minmax_commuted_f32_ieee_false:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: v_maxmin_f32 v0, v0, v1, v2
|
|
; GFX11-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: test_minmax_commuted_f32_ieee_false:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_maxmin_num_f32 v0, v0, v1, v2
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%max = call float @llvm.maxnum.f32(float %a, float %b)
|
|
%minmax = call float @llvm.minnum.f32(float %c, float %max)
|
|
ret float %minmax
|
|
}
|
|
|
|
define float @test_maxmin_f32_ieee_true(float %a, float %b, float %c) {
|
|
; SDAG-GFX11-LABEL: test_maxmin_f32_ieee_true:
|
|
; SDAG-GFX11: ; %bb.0:
|
|
; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SDAG-GFX11-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0
|
|
; SDAG-GFX11-NEXT: v_max_f32_e32 v2, v2, v2
|
|
; SDAG-GFX11-NEXT: v_minmax_f32 v0, v0, v1, v2
|
|
; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GISEL-GFX11-LABEL: test_maxmin_f32_ieee_true:
|
|
; GISEL-GFX11: ; %bb.0:
|
|
; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GISEL-GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
|
|
; GISEL-GFX11-NEXT: v_max_f32_e32 v2, v2, v2
|
|
; GISEL-GFX11-NEXT: v_minmax_f32 v0, v0, v1, v2
|
|
; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; SDAG-GFX12-LABEL: test_maxmin_f32_ieee_true:
|
|
; SDAG-GFX12: ; %bb.0:
|
|
; SDAG-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
|
|
; SDAG-GFX12-NEXT: s_wait_expcnt 0x0
|
|
; SDAG-GFX12-NEXT: s_wait_samplecnt 0x0
|
|
; SDAG-GFX12-NEXT: s_wait_bvhcnt 0x0
|
|
; SDAG-GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; SDAG-GFX12-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
|
|
; SDAG-GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2
|
|
; SDAG-GFX12-NEXT: v_minmax_num_f32 v0, v0, v1, v2
|
|
; SDAG-GFX12-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GISEL-GFX12-LABEL: test_maxmin_f32_ieee_true:
|
|
; GISEL-GFX12: ; %bb.0:
|
|
; GISEL-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
|
|
; GISEL-GFX12-NEXT: s_wait_expcnt 0x0
|
|
; GISEL-GFX12-NEXT: s_wait_samplecnt 0x0
|
|
; GISEL-GFX12-NEXT: s_wait_bvhcnt 0x0
|
|
; GISEL-GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GISEL-GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
|
|
; GISEL-GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2
|
|
; GISEL-GFX12-NEXT: v_minmax_num_f32 v0, v0, v1, v2
|
|
; GISEL-GFX12-NEXT: s_setpc_b64 s[30:31]
|
|
%min = call float @llvm.minnum.f32(float %a, float %b)
|
|
%maxmin = call float @llvm.maxnum.f32(float %min, float %c)
|
|
ret float %maxmin
|
|
}
|
|
|
|
define amdgpu_ps float @test_maxmin_commuted_f32_ieee_false(float %a, float %b, float %c) {
|
|
; GFX11-LABEL: test_maxmin_commuted_f32_ieee_false:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: v_minmax_f32 v0, v0, v1, v2
|
|
; GFX11-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: test_maxmin_commuted_f32_ieee_false:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_minmax_num_f32 v0, v0, v1, v2
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%min = call float @llvm.minnum.f32(float %a, float %b)
|
|
%maxmin = call float @llvm.maxnum.f32(float %c, float %min)
|
|
ret float %maxmin
|
|
}
|
|
|
|
define void @test_med3_f32(ptr addrspace(1) %arg, float %x, float %y, float %z) #0 {
|
|
; GFX11-LABEL: test_med3_f32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: v_med3_f32 v2, v2, v3, v4
|
|
; GFX11-NEXT: global_store_b32 v[0:1], v2, off
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX12-LABEL: test_med3_f32:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
|
|
; GFX12-NEXT: s_wait_expcnt 0x0
|
|
; GFX12-NEXT: s_wait_samplecnt 0x0
|
|
; GFX12-NEXT: s_wait_bvhcnt 0x0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: v_med3_num_f32 v2, v2, v3, v4
|
|
; GFX12-NEXT: global_store_b32 v[0:1], v2, off
|
|
; GFX12-NEXT: s_setpc_b64 s[30:31]
|
|
%tmp0 = call float @llvm.minnum.f32(float %x, float %y)
|
|
%tmp1 = call float @llvm.maxnum.f32(float %x, float %y)
|
|
%tmp2 = call float @llvm.minnum.f32(float %tmp1, float %z)
|
|
%tmp3 = call float @llvm.maxnum.f32(float %tmp0, float %tmp2)
|
|
store float %tmp3, ptr addrspace(1) %arg
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps half @test_minmax_f16_ieee_false(half %a, half %b, half %c) {
|
|
; SDAG-GFX11-TRUE16-LABEL: test_minmax_f16_ieee_false:
|
|
; SDAG-GFX11-TRUE16: ; %bb.0:
|
|
; SDAG-GFX11-TRUE16-NEXT: v_maxmin_f16 v0.l, v0.l, v1.l, v2.l
|
|
; SDAG-GFX11-TRUE16-NEXT: ; return to shader part epilog
|
|
;
|
|
; SDAG-GFX11-FAKE16-LABEL: test_minmax_f16_ieee_false:
|
|
; SDAG-GFX11-FAKE16: ; %bb.0:
|
|
; SDAG-GFX11-FAKE16-NEXT: v_maxmin_f16 v0, v0, v1, v2
|
|
; SDAG-GFX11-FAKE16-NEXT: ; return to shader part epilog
|
|
;
|
|
; GISEL-GFX11-TRUE16-LABEL: test_minmax_f16_ieee_false:
|
|
; GISEL-GFX11-TRUE16: ; %bb.0:
|
|
; GISEL-GFX11-TRUE16-NEXT: v_maxmin_f16 v0.l, v0.l, v1.l, v2.l
|
|
; GISEL-GFX11-TRUE16-NEXT: ; return to shader part epilog
|
|
;
|
|
; GISEL-GFX11-FAKE16-LABEL: test_minmax_f16_ieee_false:
|
|
; GISEL-GFX11-FAKE16: ; %bb.0:
|
|
; GISEL-GFX11-FAKE16-NEXT: v_maxmin_f16 v0, v0, v1, v2
|
|
; GISEL-GFX11-FAKE16-NEXT: ; return to shader part epilog
|
|
;
|
|
; SDAG-GFX12-TRUE16-LABEL: test_minmax_f16_ieee_false:
|
|
; SDAG-GFX12-TRUE16: ; %bb.0:
|
|
; SDAG-GFX12-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v1.l, v2.l
|
|
; SDAG-GFX12-TRUE16-NEXT: ; return to shader part epilog
|
|
;
|
|
; SDAG-GFX12-FAKE16-LABEL: test_minmax_f16_ieee_false:
|
|
; SDAG-GFX12-FAKE16: ; %bb.0:
|
|
; SDAG-GFX12-FAKE16-NEXT: v_maxmin_num_f16 v0, v0, v1, v2
|
|
; SDAG-GFX12-FAKE16-NEXT: ; return to shader part epilog
|
|
;
|
|
; GISEL-GFX12-TRUE16-LABEL: test_minmax_f16_ieee_false:
|
|
; GISEL-GFX12-TRUE16: ; %bb.0:
|
|
; GISEL-GFX12-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v1.l, v2.l
|
|
; GISEL-GFX12-TRUE16-NEXT: ; return to shader part epilog
|
|
;
|
|
; GISEL-GFX12-FAKE16-LABEL: test_minmax_f16_ieee_false:
|
|
; GISEL-GFX12-FAKE16: ; %bb.0:
|
|
; GISEL-GFX12-FAKE16-NEXT: v_maxmin_num_f16 v0, v0, v1, v2
|
|
; GISEL-GFX12-FAKE16-NEXT: ; return to shader part epilog
|
|
%max = call half @llvm.maxnum.f16(half %a, half %b)
|
|
%minmax = call half @llvm.minnum.f16(half %max, half %c)
|
|
ret half %minmax
|
|
}
|
|
|
|
define amdgpu_ps void @s_test_minmax_f16_ieee_false(half inreg %a, half inreg %b, half inreg %c, ptr addrspace(1) inreg %out) {
|
|
; SDAG-GFX11-TRUE16-LABEL: s_test_minmax_f16_ieee_false:
|
|
; SDAG-GFX11-TRUE16: ; %bb.0:
|
|
; SDAG-GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
|
|
; SDAG-GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
|
|
; SDAG-GFX11-TRUE16-NEXT: s_mov_b32 s5, s4
|
|
; SDAG-GFX11-TRUE16-NEXT: s_mov_b32 s4, s3
|
|
; SDAG-GFX11-TRUE16-NEXT: v_maxmin_f16 v0.l, s0, s1, v0.l
|
|
; SDAG-GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[4:5]
|
|
; SDAG-GFX11-TRUE16-NEXT: s_endpgm
|
|
;
|
|
; SDAG-GFX11-FAKE16-LABEL: s_test_minmax_f16_ieee_false:
|
|
; SDAG-GFX11-FAKE16: ; %bb.0:
|
|
; SDAG-GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
|
|
; SDAG-GFX11-FAKE16-NEXT: s_mov_b32 s5, s4
|
|
; SDAG-GFX11-FAKE16-NEXT: s_mov_b32 s4, s3
|
|
; SDAG-GFX11-FAKE16-NEXT: v_maxmin_f16 v0, s0, s1, v0
|
|
; SDAG-GFX11-FAKE16-NEXT: global_store_b16 v1, v0, s[4:5]
|
|
; SDAG-GFX11-FAKE16-NEXT: s_endpgm
|
|
;
|
|
; GISEL-GFX11-TRUE16-LABEL: s_test_minmax_f16_ieee_false:
|
|
; GISEL-GFX11-TRUE16: ; %bb.0:
|
|
; GISEL-GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
|
|
; GISEL-GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
|
|
; GISEL-GFX11-TRUE16-NEXT: s_mov_b32 s6, s3
|
|
; GISEL-GFX11-TRUE16-NEXT: s_mov_b32 s7, s4
|
|
; GISEL-GFX11-TRUE16-NEXT: v_maxmin_f16 v0.l, s0, s1, v0.l
|
|
; GISEL-GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[6:7]
|
|
; GISEL-GFX11-TRUE16-NEXT: s_endpgm
|
|
;
|
|
; GISEL-GFX11-FAKE16-LABEL: s_test_minmax_f16_ieee_false:
|
|
; GISEL-GFX11-FAKE16: ; %bb.0:
|
|
; GISEL-GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
|
|
; GISEL-GFX11-FAKE16-NEXT: s_mov_b32 s6, s3
|
|
; GISEL-GFX11-FAKE16-NEXT: s_mov_b32 s7, s4
|
|
; GISEL-GFX11-FAKE16-NEXT: v_maxmin_f16 v0, s0, s1, v0
|
|
; GISEL-GFX11-FAKE16-NEXT: global_store_b16 v1, v0, s[6:7]
|
|
; GISEL-GFX11-FAKE16-NEXT: s_endpgm
|
|
;
|
|
; SDAG-GFX12-TRUE16-LABEL: s_test_minmax_f16_ieee_false:
|
|
; SDAG-GFX12-TRUE16: ; %bb.0:
|
|
; SDAG-GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
|
|
; SDAG-GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
|
|
; SDAG-GFX12-TRUE16-NEXT: s_mov_b32 s5, s4
|
|
; SDAG-GFX12-TRUE16-NEXT: s_mov_b32 s4, s3
|
|
; SDAG-GFX12-TRUE16-NEXT: v_maxmin_num_f16 v0.l, s0, s1, v0.l
|
|
; SDAG-GFX12-TRUE16-NEXT: global_store_b16 v1, v0, s[4:5]
|
|
; SDAG-GFX12-TRUE16-NEXT: s_endpgm
|
|
;
|
|
; SDAG-GFX12-FAKE16-LABEL: s_test_minmax_f16_ieee_false:
|
|
; SDAG-GFX12-FAKE16: ; %bb.0:
|
|
; SDAG-GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
|
|
; SDAG-GFX12-FAKE16-NEXT: s_mov_b32 s5, s4
|
|
; SDAG-GFX12-FAKE16-NEXT: s_mov_b32 s4, s3
|
|
; SDAG-GFX12-FAKE16-NEXT: v_maxmin_num_f16 v0, s0, s1, v0
|
|
; SDAG-GFX12-FAKE16-NEXT: global_store_b16 v1, v0, s[4:5]
|
|
; SDAG-GFX12-FAKE16-NEXT: s_endpgm
|
|
;
|
|
; GISEL-GFX12-TRUE16-LABEL: s_test_minmax_f16_ieee_false:
|
|
; GISEL-GFX12-TRUE16: ; %bb.0:
|
|
; GISEL-GFX12-TRUE16-NEXT: s_max_num_f16 s0, s0, s1
|
|
; GISEL-GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
|
|
; GISEL-GFX12-TRUE16-NEXT: s_mov_b32 s6, s3
|
|
; GISEL-GFX12-TRUE16-NEXT: s_mov_b32 s7, s4
|
|
; GISEL-GFX12-TRUE16-NEXT: s_min_num_f16 s0, s0, s2
|
|
; GISEL-GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
|
|
; GISEL-GFX12-TRUE16-NEXT: global_store_b16 v1, v0, s[6:7]
|
|
; GISEL-GFX12-TRUE16-NEXT: s_endpgm
|
|
;
|
|
; GISEL-GFX12-FAKE16-LABEL: s_test_minmax_f16_ieee_false:
|
|
; GISEL-GFX12-FAKE16: ; %bb.0:
|
|
; GISEL-GFX12-FAKE16-NEXT: s_max_num_f16 s0, s0, s1
|
|
; GISEL-GFX12-FAKE16-NEXT: s_mov_b32 s6, s3
|
|
; GISEL-GFX12-FAKE16-NEXT: s_mov_b32 s7, s4
|
|
; GISEL-GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, 0
|
|
; GISEL-GFX12-FAKE16-NEXT: s_min_num_f16 s0, s0, s2
|
|
; GISEL-GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, s0
|
|
; GISEL-GFX12-FAKE16-NEXT: global_store_b16 v1, v0, s[6:7]
|
|
; GISEL-GFX12-FAKE16-NEXT: s_endpgm
|
|
%smax = call half @llvm.maxnum.f16(half %a, half %b)
|
|
%sminmax = call half @llvm.minnum.f16(half %smax, half %c)
|
|
store half %sminmax, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
define half @test_minmax_commuted_f16_ieee_true(half %a, half %b, half %c) {
|
|
; SDAG-GFX11-TRUE16-LABEL: test_minmax_commuted_f16_ieee_true:
|
|
; SDAG-GFX11-TRUE16: ; %bb.0:
|
|
; SDAG-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SDAG-GFX11-TRUE16-NEXT: v_max_f16_e32 v0.h, v1.l, v1.l
|
|
; SDAG-GFX11-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
|
|
; SDAG-GFX11-TRUE16-NEXT: v_max_f16_e32 v1.l, v2.l, v2.l
|
|
; SDAG-GFX11-TRUE16-NEXT: v_maxmin_f16 v0.l, v0.l, v0.h, v1.l
|
|
; SDAG-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; SDAG-GFX11-FAKE16-LABEL: test_minmax_commuted_f16_ieee_true:
|
|
; SDAG-GFX11-FAKE16: ; %bb.0:
|
|
; SDAG-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SDAG-GFX11-FAKE16-NEXT: v_max_f16_e32 v1, v1, v1
|
|
; SDAG-GFX11-FAKE16-NEXT: v_max_f16_e32 v0, v0, v0
|
|
; SDAG-GFX11-FAKE16-NEXT: v_max_f16_e32 v2, v2, v2
|
|
; SDAG-GFX11-FAKE16-NEXT: v_maxmin_f16 v0, v0, v1, v2
|
|
; SDAG-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GISEL-GFX11-TRUE16-LABEL: test_minmax_commuted_f16_ieee_true:
|
|
; GISEL-GFX11-TRUE16: ; %bb.0:
|
|
; GISEL-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GISEL-GFX11-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
|
|
; GISEL-GFX11-TRUE16-NEXT: v_max_f16_e32 v0.h, v1.l, v1.l
|
|
; GISEL-GFX11-TRUE16-NEXT: v_max_f16_e32 v1.l, v2.l, v2.l
|
|
; GISEL-GFX11-TRUE16-NEXT: v_maxmin_f16 v0.l, v0.l, v0.h, v1.l
|
|
; GISEL-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GISEL-GFX11-FAKE16-LABEL: test_minmax_commuted_f16_ieee_true:
|
|
; GISEL-GFX11-FAKE16: ; %bb.0:
|
|
; GISEL-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GISEL-GFX11-FAKE16-NEXT: v_max_f16_e32 v0, v0, v0
|
|
; GISEL-GFX11-FAKE16-NEXT: v_max_f16_e32 v1, v1, v1
|
|
; GISEL-GFX11-FAKE16-NEXT: v_max_f16_e32 v2, v2, v2
|
|
; GISEL-GFX11-FAKE16-NEXT: v_maxmin_f16 v0, v0, v1, v2
|
|
; GISEL-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; SDAG-GFX12-TRUE16-LABEL: test_minmax_commuted_f16_ieee_true:
|
|
; SDAG-GFX12-TRUE16: ; %bb.0:
|
|
; SDAG-GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
|
|
; SDAG-GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
|
|
; SDAG-GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
|
|
; SDAG-GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
|
|
; SDAG-GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
|
|
; SDAG-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
|
|
; SDAG-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
|
|
; SDAG-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
|
|
; SDAG-GFX12-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v0.h, v1.l
|
|
; SDAG-GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; SDAG-GFX12-FAKE16-LABEL: test_minmax_commuted_f16_ieee_true:
|
|
; SDAG-GFX12-FAKE16: ; %bb.0:
|
|
; SDAG-GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
|
|
; SDAG-GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
|
|
; SDAG-GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
|
|
; SDAG-GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
|
|
; SDAG-GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
|
|
; SDAG-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
|
|
; SDAG-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
|
|
; SDAG-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
|
|
; SDAG-GFX12-FAKE16-NEXT: v_maxmin_num_f16 v0, v0, v1, v2
|
|
; SDAG-GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GISEL-GFX12-TRUE16-LABEL: test_minmax_commuted_f16_ieee_true:
|
|
; GISEL-GFX12-TRUE16: ; %bb.0:
|
|
; GISEL-GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
|
|
; GISEL-GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
|
|
; GISEL-GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
|
|
; GISEL-GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
|
|
; GISEL-GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
|
|
; GISEL-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
|
|
; GISEL-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
|
|
; GISEL-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
|
|
; GISEL-GFX12-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v0.h, v1.l
|
|
; GISEL-GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GISEL-GFX12-FAKE16-LABEL: test_minmax_commuted_f16_ieee_true:
|
|
; GISEL-GFX12-FAKE16: ; %bb.0:
|
|
; GISEL-GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
|
|
; GISEL-GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
|
|
; GISEL-GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
|
|
; GISEL-GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
|
|
; GISEL-GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
|
|
; GISEL-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
|
|
; GISEL-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
|
|
; GISEL-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
|
|
; GISEL-GFX12-FAKE16-NEXT: v_maxmin_num_f16 v0, v0, v1, v2
|
|
; GISEL-GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%max = call half @llvm.maxnum.f16(half %a, half %b)
|
|
%minmax = call half @llvm.minnum.f16(half %c, half %max)
|
|
ret half %minmax
|
|
}
|
|
|
|
define amdgpu_ps half @test_maxmin_f16_ieee_false(half %a, half %b, half %c) {
|
|
; SDAG-GFX11-TRUE16-LABEL: test_maxmin_f16_ieee_false:
|
|
; SDAG-GFX11-TRUE16: ; %bb.0:
|
|
; SDAG-GFX11-TRUE16-NEXT: v_minmax_f16 v0.l, v0.l, v1.l, v2.l
|
|
; SDAG-GFX11-TRUE16-NEXT: ; return to shader part epilog
|
|
;
|
|
; SDAG-GFX11-FAKE16-LABEL: test_maxmin_f16_ieee_false:
|
|
; SDAG-GFX11-FAKE16: ; %bb.0:
|
|
; SDAG-GFX11-FAKE16-NEXT: v_minmax_f16 v0, v0, v1, v2
|
|
; SDAG-GFX11-FAKE16-NEXT: ; return to shader part epilog
|
|
;
|
|
; GISEL-GFX11-TRUE16-LABEL: test_maxmin_f16_ieee_false:
|
|
; GISEL-GFX11-TRUE16: ; %bb.0:
|
|
; GISEL-GFX11-TRUE16-NEXT: v_minmax_f16 v0.l, v0.l, v1.l, v2.l
|
|
; GISEL-GFX11-TRUE16-NEXT: ; return to shader part epilog
|
|
;
|
|
; GISEL-GFX11-FAKE16-LABEL: test_maxmin_f16_ieee_false:
|
|
; GISEL-GFX11-FAKE16: ; %bb.0:
|
|
; GISEL-GFX11-FAKE16-NEXT: v_minmax_f16 v0, v0, v1, v2
|
|
; GISEL-GFX11-FAKE16-NEXT: ; return to shader part epilog
|
|
;
|
|
; SDAG-GFX12-TRUE16-LABEL: test_maxmin_f16_ieee_false:
|
|
; SDAG-GFX12-TRUE16: ; %bb.0:
|
|
; SDAG-GFX12-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v1.l, v2.l
|
|
; SDAG-GFX12-TRUE16-NEXT: ; return to shader part epilog
|
|
;
|
|
; SDAG-GFX12-FAKE16-LABEL: test_maxmin_f16_ieee_false:
|
|
; SDAG-GFX12-FAKE16: ; %bb.0:
|
|
; SDAG-GFX12-FAKE16-NEXT: v_minmax_num_f16 v0, v0, v1, v2
|
|
; SDAG-GFX12-FAKE16-NEXT: ; return to shader part epilog
|
|
;
|
|
; GISEL-GFX12-TRUE16-LABEL: test_maxmin_f16_ieee_false:
|
|
; GISEL-GFX12-TRUE16: ; %bb.0:
|
|
; GISEL-GFX12-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v1.l, v2.l
|
|
; GISEL-GFX12-TRUE16-NEXT: ; return to shader part epilog
|
|
;
|
|
; GISEL-GFX12-FAKE16-LABEL: test_maxmin_f16_ieee_false:
|
|
; GISEL-GFX12-FAKE16: ; %bb.0:
|
|
; GISEL-GFX12-FAKE16-NEXT: v_minmax_num_f16 v0, v0, v1, v2
|
|
; GISEL-GFX12-FAKE16-NEXT: ; return to shader part epilog
|
|
%min = call half @llvm.minnum.f16(half %a, half %b)
|
|
%maxmin = call half @llvm.maxnum.f16(half %min, half %c)
|
|
ret half %maxmin
|
|
}
|
|
|
|
define half @test_maxmin_commuted_f16_ieee_true(half %a, half %b, half %c) {
|
|
; SDAG-GFX11-TRUE16-LABEL: test_maxmin_commuted_f16_ieee_true:
|
|
; SDAG-GFX11-TRUE16: ; %bb.0:
|
|
; SDAG-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SDAG-GFX11-TRUE16-NEXT: v_max_f16_e32 v0.h, v1.l, v1.l
|
|
; SDAG-GFX11-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
|
|
; SDAG-GFX11-TRUE16-NEXT: v_max_f16_e32 v1.l, v2.l, v2.l
|
|
; SDAG-GFX11-TRUE16-NEXT: v_minmax_f16 v0.l, v0.l, v0.h, v1.l
|
|
; SDAG-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; SDAG-GFX11-FAKE16-LABEL: test_maxmin_commuted_f16_ieee_true:
|
|
; SDAG-GFX11-FAKE16: ; %bb.0:
|
|
; SDAG-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SDAG-GFX11-FAKE16-NEXT: v_max_f16_e32 v1, v1, v1
|
|
; SDAG-GFX11-FAKE16-NEXT: v_max_f16_e32 v0, v0, v0
|
|
; SDAG-GFX11-FAKE16-NEXT: v_max_f16_e32 v2, v2, v2
|
|
; SDAG-GFX11-FAKE16-NEXT: v_minmax_f16 v0, v0, v1, v2
|
|
; SDAG-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GISEL-GFX11-TRUE16-LABEL: test_maxmin_commuted_f16_ieee_true:
|
|
; GISEL-GFX11-TRUE16: ; %bb.0:
|
|
; GISEL-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GISEL-GFX11-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
|
|
; GISEL-GFX11-TRUE16-NEXT: v_max_f16_e32 v0.h, v1.l, v1.l
|
|
; GISEL-GFX11-TRUE16-NEXT: v_max_f16_e32 v1.l, v2.l, v2.l
|
|
; GISEL-GFX11-TRUE16-NEXT: v_minmax_f16 v0.l, v0.l, v0.h, v1.l
|
|
; GISEL-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GISEL-GFX11-FAKE16-LABEL: test_maxmin_commuted_f16_ieee_true:
|
|
; GISEL-GFX11-FAKE16: ; %bb.0:
|
|
; GISEL-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GISEL-GFX11-FAKE16-NEXT: v_max_f16_e32 v0, v0, v0
|
|
; GISEL-GFX11-FAKE16-NEXT: v_max_f16_e32 v1, v1, v1
|
|
; GISEL-GFX11-FAKE16-NEXT: v_max_f16_e32 v2, v2, v2
|
|
; GISEL-GFX11-FAKE16-NEXT: v_minmax_f16 v0, v0, v1, v2
|
|
; GISEL-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; SDAG-GFX12-TRUE16-LABEL: test_maxmin_commuted_f16_ieee_true:
|
|
; SDAG-GFX12-TRUE16: ; %bb.0:
|
|
; SDAG-GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
|
|
; SDAG-GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
|
|
; SDAG-GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
|
|
; SDAG-GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
|
|
; SDAG-GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
|
|
; SDAG-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
|
|
; SDAG-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
|
|
; SDAG-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
|
|
; SDAG-GFX12-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v0.h, v1.l
|
|
; SDAG-GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; SDAG-GFX12-FAKE16-LABEL: test_maxmin_commuted_f16_ieee_true:
|
|
; SDAG-GFX12-FAKE16: ; %bb.0:
|
|
; SDAG-GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
|
|
; SDAG-GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
|
|
; SDAG-GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
|
|
; SDAG-GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
|
|
; SDAG-GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
|
|
; SDAG-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
|
|
; SDAG-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
|
|
; SDAG-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
|
|
; SDAG-GFX12-FAKE16-NEXT: v_minmax_num_f16 v0, v0, v1, v2
|
|
; SDAG-GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GISEL-GFX12-TRUE16-LABEL: test_maxmin_commuted_f16_ieee_true:
|
|
; GISEL-GFX12-TRUE16: ; %bb.0:
|
|
; GISEL-GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
|
|
; GISEL-GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
|
|
; GISEL-GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
|
|
; GISEL-GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
|
|
; GISEL-GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
|
|
; GISEL-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
|
|
; GISEL-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
|
|
; GISEL-GFX12-TRUE16-NEXT: v_max_num_f16_e32 v1.l, v2.l, v2.l
|
|
; GISEL-GFX12-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v0.h, v1.l
|
|
; GISEL-GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GISEL-GFX12-FAKE16-LABEL: test_maxmin_commuted_f16_ieee_true:
|
|
; GISEL-GFX12-FAKE16: ; %bb.0:
|
|
; GISEL-GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
|
|
; GISEL-GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
|
|
; GISEL-GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
|
|
; GISEL-GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
|
|
; GISEL-GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
|
|
; GISEL-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v0
|
|
; GISEL-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v1, v1, v1
|
|
; GISEL-GFX12-FAKE16-NEXT: v_max_num_f16_e32 v2, v2, v2
|
|
; GISEL-GFX12-FAKE16-NEXT: v_minmax_num_f16 v0, v0, v1, v2
|
|
; GISEL-GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%min = call half @llvm.minnum.f16(half %a, half %b)
|
|
%maxmin = call half @llvm.maxnum.f16(half %c, half %min)
|
|
ret half %maxmin
|
|
}
|
|
|
|
define void @test_med3_f16(ptr addrspace(1) %arg, half %x, half %y, half %z) #0 {
|
|
; SDAG-GFX11-TRUE16-LABEL: test_med3_f16:
|
|
; SDAG-GFX11-TRUE16: ; %bb.0:
|
|
; SDAG-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SDAG-GFX11-TRUE16-NEXT: v_med3_f16 v2.l, v2.l, v3.l, v4.l
|
|
; SDAG-GFX11-TRUE16-NEXT: global_store_b16 v[0:1], v2, off
|
|
; SDAG-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; SDAG-GFX11-FAKE16-LABEL: test_med3_f16:
|
|
; SDAG-GFX11-FAKE16: ; %bb.0:
|
|
; SDAG-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SDAG-GFX11-FAKE16-NEXT: v_med3_f16 v2, v2, v3, v4
|
|
; SDAG-GFX11-FAKE16-NEXT: global_store_b16 v[0:1], v2, off
|
|
; SDAG-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GISEL-GFX11-TRUE16-LABEL: test_med3_f16:
|
|
; GISEL-GFX11-TRUE16: ; %bb.0:
|
|
; GISEL-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GISEL-GFX11-TRUE16-NEXT: v_med3_f16 v2.l, v2.l, v3.l, v4.l
|
|
; GISEL-GFX11-TRUE16-NEXT: global_store_b16 v[0:1], v2, off
|
|
; GISEL-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GISEL-GFX11-FAKE16-LABEL: test_med3_f16:
|
|
; GISEL-GFX11-FAKE16: ; %bb.0:
|
|
; GISEL-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GISEL-GFX11-FAKE16-NEXT: v_med3_f16 v2, v2, v3, v4
|
|
; GISEL-GFX11-FAKE16-NEXT: global_store_b16 v[0:1], v2, off
|
|
; GISEL-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; SDAG-GFX12-TRUE16-LABEL: test_med3_f16:
|
|
; SDAG-GFX12-TRUE16: ; %bb.0:
|
|
; SDAG-GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
|
|
; SDAG-GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
|
|
; SDAG-GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
|
|
; SDAG-GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
|
|
; SDAG-GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
|
|
; SDAG-GFX12-TRUE16-NEXT: v_med3_num_f16 v2.l, v2.l, v3.l, v4.l
|
|
; SDAG-GFX12-TRUE16-NEXT: global_store_b16 v[0:1], v2, off
|
|
; SDAG-GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; SDAG-GFX12-FAKE16-LABEL: test_med3_f16:
|
|
; SDAG-GFX12-FAKE16: ; %bb.0:
|
|
; SDAG-GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
|
|
; SDAG-GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
|
|
; SDAG-GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
|
|
; SDAG-GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
|
|
; SDAG-GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
|
|
; SDAG-GFX12-FAKE16-NEXT: v_med3_num_f16 v2, v2, v3, v4
|
|
; SDAG-GFX12-FAKE16-NEXT: global_store_b16 v[0:1], v2, off
|
|
; SDAG-GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GISEL-GFX12-TRUE16-LABEL: test_med3_f16:
|
|
; GISEL-GFX12-TRUE16: ; %bb.0:
|
|
; GISEL-GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
|
|
; GISEL-GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
|
|
; GISEL-GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
|
|
; GISEL-GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
|
|
; GISEL-GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
|
|
; GISEL-GFX12-TRUE16-NEXT: v_med3_num_f16 v2.l, v2.l, v3.l, v4.l
|
|
; GISEL-GFX12-TRUE16-NEXT: global_store_b16 v[0:1], v2, off
|
|
; GISEL-GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GISEL-GFX12-FAKE16-LABEL: test_med3_f16:
|
|
; GISEL-GFX12-FAKE16: ; %bb.0:
|
|
; GISEL-GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
|
|
; GISEL-GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
|
|
; GISEL-GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
|
|
; GISEL-GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
|
|
; GISEL-GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
|
|
; GISEL-GFX12-FAKE16-NEXT: v_med3_num_f16 v2, v2, v3, v4
|
|
; GISEL-GFX12-FAKE16-NEXT: global_store_b16 v[0:1], v2, off
|
|
; GISEL-GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%tmp0 = call half @llvm.minnum.f16(half %x, half %y)
|
|
%tmp1 = call half @llvm.maxnum.f16(half %x, half %y)
|
|
%tmp2 = call half @llvm.minnum.f16(half %tmp1, half %z)
|
|
%tmp3 = call half @llvm.maxnum.f16(half %tmp0, half %tmp2)
|
|
store half %tmp3, ptr addrspace(1) %arg
|
|
ret void
|
|
}
|
|
|
|
declare i32 @llvm.smin.i32(i32, i32)
|
|
declare i32 @llvm.smax.i32(i32, i32)
|
|
declare i32 @llvm.umin.i32(i32, i32)
|
|
declare i32 @llvm.umax.i32(i32, i32)
|
|
declare half @llvm.minnum.f16(half, half)
|
|
declare half @llvm.maxnum.f16(half, half)
|
|
declare float @llvm.minnum.f32(float, float)
|
|
declare float @llvm.maxnum.f32(float, float)
|
|
attributes #0 = { nounwind "unsafe-fp-math"="false" "no-nans-fp-math"="true" }
|
|
|