60a8b2b1d0
Addition of a check in the MachineVerifier to detect and report illegal vector registers to SGPR copies in the AMDGPU backend, ensuring correct code generation. We can enforce this check only after SIFixSGPRCopies pass. This is half-fix in the pipeline with the help of isSSA MachineFuction property, the check is happening for passes after phi-node-elimination.
170 lines
5.3 KiB
YAML
170 lines
5.3 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=si-fix-sgpr-copies -o - %s | FileCheck -check-prefix=GCN %s
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---
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name: phi_moveimm_input
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tracksRegLiveness: true
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body: |
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; GCN-LABEL: name: phi_moveimm_input
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; GCN: bb.0:
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; GCN-NEXT: successors: %bb.1(0x80000000)
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; GCN-NEXT: liveins: $sgpr0, $sgpr1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.1:
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; GCN-NEXT: successors: %bb.2(0x80000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
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; GCN-NEXT: S_BRANCH %bb.2
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.2:
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; GCN-NEXT: successors: %bb.3(0x80000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[PHI:%[0-9]+]]:sreg_32 = PHI %5, %bb.3, [[S_ADD_U32_]], %bb.1
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; GCN-NEXT: S_BRANCH %bb.3
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.3:
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; GCN-NEXT: successors: %bb.2(0x80000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GCN-NEXT: S_BRANCH %bb.2
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bb.0:
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successors: %bb.1
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liveins: $sgpr0, $sgpr1
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%0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%4:sreg_32 = COPY $sgpr0
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%5:sreg_32 = COPY $sgpr1
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bb.1:
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successors: %bb.2
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%2:sreg_32 = S_ADD_U32 %4, %5, implicit-def $scc
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S_BRANCH %bb.2
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bb.2:
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successors: %bb.3
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%3:sreg_32 = PHI %1, %bb.3, %2, %bb.1
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S_BRANCH %bb.3
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bb.3:
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successors: %bb.2
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%1:sreg_32 = COPY %0
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S_BRANCH %bb.2
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...
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---
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name: phi_moveimm_subreg_input
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tracksRegLiveness: true
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body: |
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; GCN-LABEL: name: phi_moveimm_subreg_input
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; GCN: bb.0:
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; GCN-NEXT: successors: %bb.1(0x80000000)
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; GCN-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[V_MOV_B64_e32_:%[0-9]+]]:vreg_64 = V_MOV_B64_e32 0, implicit $exec
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.1:
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; GCN-NEXT: successors: %bb.2(0x80000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[S_ADD_U:%[0-9]+]]:sreg_64 = S_ADD_U64_PSEUDO [[COPY]], [[COPY1]], implicit-def $scc
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; GCN-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[S_ADD_U]], implicit $exec
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; GCN-NEXT: S_BRANCH %bb.2
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.2:
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; GCN-NEXT: successors: %bb.3(0x80000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[V_MOV_B64_e32_]].sub0, %bb.3, [[COPY2]].sub0, %bb.1
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; GCN-NEXT: S_BRANCH %bb.3
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.3:
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; GCN-NEXT: successors: %bb.2(0x80000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
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; GCN-NEXT: S_BRANCH %bb.2
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bb.0:
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successors: %bb.1
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liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
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%0:vreg_64 = V_MOV_B64_e32 0, implicit $exec
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%4:sreg_64 = COPY $sgpr0_sgpr1
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%5:sreg_64 = COPY $sgpr2_sgpr3
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bb.1:
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successors: %bb.2
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%2:sreg_64 = S_ADD_U64_PSEUDO %4, %5, implicit-def $scc
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S_BRANCH %bb.2
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bb.2:
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successors: %bb.3
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%3:sreg_32 = PHI %1.sub0:sreg_64, %bb.3, %2.sub0:sreg_64, %bb.1
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S_BRANCH %bb.3
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bb.3:
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successors: %bb.2
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%1:sreg_64 = COPY %0.sub0:vreg_64
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S_BRANCH %bb.2
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...
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---
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name: phi_moveimm_bad_opcode_input
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tracksRegLiveness: true
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body: |
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; GCN-LABEL: name: phi_moveimm_bad_opcode_input
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; GCN: bb.0:
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; GCN-NEXT: successors: %bb.1(0x80000000)
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; GCN-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN-NEXT: [[V_MOV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_MOV_B32_sdwa 0, [[COPY]], 0, 5, 2, 4, implicit $exec, implicit [[COPY]](tied-def 0)
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; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.1:
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; GCN-NEXT: successors: %bb.2(0x80000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[COPY2]], implicit-def $scc
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; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_U32_]], implicit $exec
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; GCN-NEXT: S_BRANCH %bb.2
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.2:
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; GCN-NEXT: successors: %bb.3(0x80000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[V_MOV_B32_sdwa]], %bb.3, [[COPY3]], %bb.1
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; GCN-NEXT: S_BRANCH %bb.3
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.3:
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; GCN-NEXT: successors: %bb.2(0x80000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
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; GCN-NEXT: S_BRANCH %bb.2
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bb.0:
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successors: %bb.1
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liveins: $sgpr0, $sgpr1, $vgpr0
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%6:vgpr_32 = COPY $vgpr0
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%0:vgpr_32 = V_MOV_B32_sdwa 0, %6:vgpr_32, 0, 5, 2, 4, implicit $exec, implicit %6:vgpr_32(tied-def 0)
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%4:sreg_32 = COPY $sgpr0
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%5:sreg_32 = COPY $sgpr1
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bb.1:
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successors: %bb.2
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%2:sreg_32 = S_ADD_U32 %4, %5, implicit-def $scc
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S_BRANCH %bb.2
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bb.2:
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successors: %bb.3
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%3:sreg_32 = PHI %1, %bb.3, %2, %bb.1
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S_BRANCH %bb.3
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bb.3:
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successors: %bb.2
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%1:sreg_32 = COPY %0
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S_BRANCH %bb.2
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...
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