ed3597e2f7
There are two classes of operands that DecoderEmitter cannot currently
handle:
1. Operands that do not participate in instruction encoding.
2. Operands whose encoding contains only 1s and 0s.
Because of this, targets developed various workarounds. Some targets
insert missing operands after an instruction has been (incompletely)
decoded, other take into account the missing operands when printing the
instruction. Some targets do neither of that and fail to correctly
disassemble some instructions.
This patch makes it possible to decode both classes of operands and
allows to remove existing workarounds.
For the case of operand with no contribution to instruction encoding,
one should now add `bits<0> OpName` field to instruction encoding
record. This will make DecoderEmitter generate a call to the decoder
function specified by the operand's DecoderMethod. The function has a
signature different from the usual one and looks like this:
```
static DecodeStatus DecodeImm42Operand(MCInst &Inst, const MCDisassembler *Decoder) {
Inst.addOperand(MCOperand::createImm(42));
return DecodeStatus::Success;
}
```
Notably, encoding bits are not passed to it (since there are none).
There is nothing special about the second case, the operand bits are
passed as usual. The difference is that before this change, the function
was not called if all the bits of the operand were known (no '?' in the
operand encoding).
There are two options controlling the behavior. Passing an option
enables the old behavior. They exist to allow smooth transition to the
new behavior. They are temporary (yeah, I know) and will be removed once
all targets migrate, possibly giving some more time to downstream
targets.
Subsequent patches in the stack enable the new behavior on some in-tree
targets.
109 lines
4.6 KiB
TableGen
109 lines
4.6 KiB
TableGen
// RUN: llvm-tblgen -gen-disassembler -ignore-non-decodable-operands -I %p/../../include %s | \
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// RUN: FileCheck --check-prefix=DISASS %s
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// RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s | \
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// RUN: FileCheck --check-prefix=MATCHER %s
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// RUN: llvm-tblgen -gen-asm-writer -I %p/../../include %s | \
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// RUN: FileCheck --check-prefix=WRITER %s
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// Check that combining conditions in AssemblerPredicate generates the correct
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// output when using both the (all_of) AND operator, and the (any_of) OR
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// operator.
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include "llvm/Target/Target.td"
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def archInstrInfo : InstrInfo { }
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def archAsmWriter : AsmWriter {
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int PassSubtarget = 1;
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}
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def arch : Target {
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let InstructionSet = archInstrInfo;
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let AssemblyWriters = [archAsmWriter];
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}
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let Namespace = "arch" in {
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def R0 : Register<"r0">;
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def R1 : Register<"r1">;
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def R2 : Register<"r2">;
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def R3 : Register<"r3">;
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def R4 : Register<"r4">;
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}
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def Regs : RegisterClass<"Regs", [i32], 32, (add R0, R1, R2, R3, R4)>;
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class TestInsn<int Opc, list<Predicate> Preds> : Instruction {
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let Size = 2;
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let OutOperandList = (outs);
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let InOperandList = (ins Regs:$r);
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field bits<16> Inst;
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let Inst = Opc;
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let AsmString = NAME # " $r";
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field bits<16> SoftFail = 0;
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let Predicates = Preds;
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}
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def AsmCond1 : SubtargetFeature<"cond1", "cond1", "true", "">;
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def AsmCond2a: SubtargetFeature<"cond2a", "cond2a", "true", "">;
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def AsmCond2b: SubtargetFeature<"cond2b", "cond2b", "true", "">;
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def AsmCond3a: SubtargetFeature<"cond3a", "cond3a", "true", "">;
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def AsmCond3b: SubtargetFeature<"cond3b", "cond3b", "true", "">;
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def AsmCond4 : SubtargetFeature<"cond4", "cond4", "true", "">;
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def AsmPred1 : Predicate<"Pred1">, AssemblerPredicate<(all_of AsmCond1)>;
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def AsmPred2 : Predicate<"Pred2">, AssemblerPredicate<(all_of AsmCond2a, AsmCond2b)>;
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def AsmPred3 : Predicate<"Pred3">, AssemblerPredicate<(any_of AsmCond3a, AsmCond3b)>;
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def AsmPred4 : Predicate<"Pred4">, AssemblerPredicate<(all_of AsmCond4, (not (any_of AsmCond3a, AsmCond3b)))>;
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// MATCHER: if (FB[arch::AsmCond1])
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// MATCHER-NEXT: Features.set(Feature_AsmPred1Bit);
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// MATCHER-NEXT: if (FB[arch::AsmCond2a] && FB[arch::AsmCond2b])
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// MATCHER-NEXT: Features.set(Feature_AsmPred2Bit);
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// MATCHER-NEXT: if (FB[arch::AsmCond3a] || FB[arch::AsmCond3b])
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// MATCHER-NEXT: Features.set(Feature_AsmPred3Bit);
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// MATCHER-NEXT: if (FB[arch::AsmCond4] && !(FB[arch::AsmCond3a] || FB[arch::AsmCond3b]))
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// MATCHER-NEXT: Features.set(Feature_AsmPred4Bit);
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def insn1 : TestInsn<1, [AsmPred1]>;
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// DISASS: return (Bits[arch::AsmCond1]);
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def insn2 : TestInsn<2, [AsmPred2]>;
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// DISASS: return (Bits[arch::AsmCond2a] && Bits[arch::AsmCond2b])
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def insn3 : TestInsn<3, [AsmPred3]>;
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// DISASS: return (Bits[arch::AsmCond3a] || Bits[arch::AsmCond3b])
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def insn4 : TestInsn<4, [AsmPred1, AsmPred2]>;
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// DISASS: return (Bits[arch::AsmCond1] && (Bits[arch::AsmCond2a] && Bits[arch::AsmCond2b]))
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def insn5 : TestInsn<5, [AsmPred1, AsmPred3]>;
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// DISASS: return (Bits[arch::AsmCond1] && (Bits[arch::AsmCond3a] || Bits[arch::AsmCond3b]))
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def insn6 : TestInsn<6, []>;
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def : InstAlias<"alias1", (insn6 R0)> { let Predicates = [AsmPred1]; }
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// WRITER: // (insn6 R0)
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// WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R0},
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// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond1},
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def : InstAlias<"alias2", (insn6 R1)> { let Predicates = [AsmPred2]; }
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// WRITER: // (insn6 R1)
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// WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R1},
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// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond2a},
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// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond2b},
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def : InstAlias<"alias3", (insn6 R2)> { let Predicates = [AsmPred3]; }
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// WRITER: // (insn6 R2)
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// WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R2},
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// WRITER-NEXT: {AliasPatternCond::K_OrFeature, arch::AsmCond3a},
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// WRITER-NEXT: {AliasPatternCond::K_OrFeature, arch::AsmCond3b},
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// WRITER-NEXT: {AliasPatternCond::K_EndOrFeatures, 0},
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def : InstAlias<"alias4", (insn6 R3)> { let Predicates = [AsmPred1, AsmPred2]; }
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// WRITER: // (insn6 R3)
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// WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R3},
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// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond1},
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// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond2a},
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// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond2b},
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def : InstAlias<"alias5", (insn6 R4)> { let Predicates = [AsmPred1, AsmPred3]; }
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// WRITER: // (insn6 R4)
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// WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R4},
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// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond1},
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// WRITER-NEXT: {AliasPatternCond::K_OrFeature, arch::AsmCond3a},
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// WRITER-NEXT: {AliasPatternCond::K_OrFeature, arch::AsmCond3b},
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// WRITER-NEXT: {AliasPatternCond::K_EndOrFeatures, 0},
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