dafffe262d
This change adds an option to specialize decoders per bitwidth, which can help reduce the (compiled) code size of the decoder code. **Current state**: Currently, the code generated by the decoder emitter consists of two key functions: `decodeInstruction` which is the entry point into the generated code and `decodeToMCInst` which is invoked when a decode op is reached while traversing through the decoder table. Both functions are templated on `InsnType` which is the raw instruction bits that are supplied to `decodeInstruction`. Several backends call `decodeInstruction` with different `InsnType` types, leading to several template instantiations of these functions in the final code. As an example, AMDGPU instantiates this function with type `DecoderUInt128` type for decoding 96/128-bit instructions, `uint64_t` for decoding 64-bit instructions, and `uint32_t` for decoding 32-bit instructions. Since there is just one `decodeToMCInst` in the generated code, it has code that handles decoding for *all* instruction sizes. However, the decoders emitted for different instructions sizes rarely have any intersection with each other. That means, in the AMDGPU case, the instantiation with InsnType == DecoderUInt128 has decoder code for 32/64-bit instructions that is *never exercised*. Conversely, the instantiation with InsnType == uint64_t has decoder code for 128/96/32-bit instructions that is never exercised. This leads to unnecessary dead code in the generated disassembler binary (that the compiler cannot eliminate by itself). **New state**: With this change, we introduce an option `specialize-decoders-per-bitwidth`. Under this mode, the DecoderEmitter will generate several versions of `decodeToMCInst` function, one for each bitwidth. The code is still templated, but will require backends to specify, for each `InsnType` used, the bitwidth of the instruction that the type is used to represent using a type-trait `InsnBitWidth`. This will enable the templated code to choose the right variant of `decodeToMCInst`. Under this mode, a particular instantiation will only end up instantiating a single variant of `decodeToMCInst` generated and that will include only those decoders that are applicable to a single bitwidth, resulting in elimination of the code duplication through instantiation and a reduction in code size. Additionally, under this mode, decoders are uniqued only within a given bitwidth (as opposed to across all bitwidths without this option), so the decoder index values assigned are smaller, and consume less bytes in their ULEB128 encoding. As a result, the generated decoder tables can also reduce in size. Adopt this feature for the AMDGPU and RISCV backend. In a release build, this results in a net 55% reduction in the .text size of libLLVMAMDGPUDisassembler.so and a 5% reduction in the .rodata size. For RISCV, which today uses a single `uint64_t` type, this results in a 3.7% increase in code size (expected as we instantiate the code 3 times now). Actual measured sizes are as follows: ``` Baseline commit: 72c04bb882ad70230bce309c3013d9cc2c99e9a7 Configuration: Ubuntu clang version 18.1.3, release build with asserts disabled. AMDGPU Before After Change ====================================================== .text 612327 275607 55% reduction .rodata 369728 351336 5% reduction RISCV: ====================================================== .text 47407 49187 3.7% increase .rodata 35768 35839 0.1% increase ```
85 lines
2.8 KiB
TableGen
85 lines
2.8 KiB
TableGen
// RUN: llvm-tblgen -gen-disassembler -use-fn-table-in-decode-to-mcinst -I %p/../../include %s | FileCheck %s
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include "llvm/Target/Target.td"
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def archInstrInfo : InstrInfo { }
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def arch : Target {
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let InstructionSet = archInstrInfo;
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}
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let Namespace = "arch" in {
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def R0 : Register<"r0">;
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def R1 : Register<"r1">;
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def R2 : Register<"r2">;
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def R3 : Register<"r3">;
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}
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def Regs : RegisterClass<"Regs", [i32], 32, (add R0, R1, R2, R3)>;
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class TestInstruction : Instruction {
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let Size = 1;
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let OutOperandList = (outs);
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field bits<8> Inst;
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field bits<8> SoftFail = 0;
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}
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// Define instructions to generate 4 cases in decodeToMCInst.
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// Lower 2 bits define the number of operands. Each register operand
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// needs 2 bits to encode.
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// An instruction with no inputs. Encoded with lower 2 bits = 0 and upper
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// 6 bits = 0 as well.
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def Inst0 : TestInstruction {
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let Inst = 0x0;
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let InOperandList = (ins);
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let AsmString = "Inst0";
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}
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// An instruction with a single input. Encoded with lower 2 bits = 1 and the
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// single input in bits 2-3.
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def Inst1 : TestInstruction {
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bits<2> r0;
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let Inst{1-0} = 1;
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let Inst{3-2} = r0;
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let InOperandList = (ins Regs:$r0);
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let AsmString = "Inst1";
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}
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// An instruction with two inputs. Encoded with lower 2 bits = 2 and the
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// inputs in bits 2-3 and 4-5.
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def Inst2 : TestInstruction {
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bits<2> r0;
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bits<2> r1;
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let Inst{1-0} = 2;
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let Inst{3-2} = r0;
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let Inst{5-4} = r1;
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let InOperandList = (ins Regs:$r0, Regs:$r1);
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let AsmString = "Inst2";
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}
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// An instruction with three inputs. Encoded with lower 2 bits = 3 and the
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// inputs in bits 2-3 and 4-5 and 6-7.
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def Inst3 : TestInstruction {
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bits<2> r0;
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bits<2> r1;
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bits<2> r2;
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let Inst{1-0} = 3;
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let Inst{3-2} = r0;
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let Inst{5-4} = r1;
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let Inst{7-6} = r2;
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let InOperandList = (ins Regs:$r0, Regs:$r1, Regs:$r2);
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let AsmString = "Inst3";
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}
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// CHECK-LABEL: DecodeStatus decodeFn_0(DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete)
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// CHECK-LABEL: DecodeStatus decodeFn_1(DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete)
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// CHECK-LABEL: DecodeStatus decodeFn_2(DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete)
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// CHECK-LABEL: DecodeStatus decodeFn_3(DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete)
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// CHECK-LABEL: decodeToMCInst(unsigned Idx, DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete)
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// CHECK: static constexpr DecodeFnTy decodeFnTable[]
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// CHECK-NEXT: decodeFn_0,
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// CHECK-NEXT: decodeFn_1,
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// CHECK-NEXT: decodeFn_2,
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// CHECK-NEXT: decodeFn_3,
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// CHECK: return decodeFnTable[Idx](S, insn, MI, Address, Decoder, DecodeComplete)
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