llvm-project

History

yanming 8d9d8f866a [RISCV] Define risc-v's own register class to model FP Register.

The default RegisterClass is not enough to model RISCV Register.
We define risc-v's own register class to model FP Register.
This helps to better estimate the register pressure in the loop-vectorize.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D126854

2022-06-06 14:43:52 +08:00

lit.local.cfg

…

low-trip-count.ll

[LoopVectorize] Permit tail-folding for low trip counts using scalable vectors

2022-05-16 09:14:24 +01:00

masked_gather_scatter.ll

[RISCV] Remove experimental prefix from rvv-related extensions.

2022-01-22 20:18:40 -08:00

reg-usage.ll

[RISCV] Define risc-v's own register class to model FP Register.

2022-06-06 14:43:52 +08:00